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Designing With the UltraScale Architecture

This course introduces new and experienced designers to the most sophisticated aspects of the UltraScale architecture. Targeted towards designers who have used the Vivado Design Suite, this course focuses on designing for the new and enhanced resources found in our newest FPGA family.

Topics covered include device overviews, CLB resources, MMCM and PLL clock management resources, global and regional clocking resources, memory and DSP resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Generator (MIG) and the new DDR4 memory interface capabilities is also covered.