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Designing w/ UltraScale & UltraScale+ Architectures

This course introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers. The emphasis is on: ▪ Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources ▪ Describing improvements to the dedicated transceivers and Transceiver Wizard ▪ Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities ▪ Migrating existing designs and IP to the UltraScale architecture with optimal use of the Vivado® Design Suite What's New for 2021.2 ▪ All labs have been updated to the latest software versions.