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How to Design a High Speed Memory Interface

2015.1 This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. The emphasis is on: ▪ Introducing the basic concepts of high-speed memory I/O design, implementation, and debug using Xilinx 7 series FPGAs. ▪ Learning about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces. The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR2, and QDRII+. Labs are available for DDR3 on the Kintex®-7 FPGA KC705 board.

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How to Design High-Speed Memory Interface, July 13-14 Online
$1,600.00

Title: How to Design a High-Speed Memory Interface
Date/Duration: July 13-14 2021 Two days
Times: 9 AM - 5 PM CST
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