Designing with the Versal ACAP: Architecture and Methodology

This course helps you to learn about Versal® ACAP architecture and design methodology. The emphasis of this course is on: ▪ Reviewing the architecture of the Versal ACAP ▪ Describing the different engines available in the Versal architecture and what resources they contain ▪ Utilizing the hardened blocks available in the Versal architecture ▪ Using the design tools and methodology provided by Xilinx to create complex systems ▪ Describing the network on chip (NoC) and AI Engine concepts and their architectures ▪ Performing system-level simulation and debugging What's New for 2022.1 ▪ Introduced Versal HBM series and comparison for device resources among different Versal series devices ▪ Updated information on primary and secondary boot modes and PLM libraries ▪ Added information on asymmetric hardware root of trust and symmetric hardware root of trust ▪ Added information on high bandwidth memory interfaces ▪ Added information on power awareness ▪ All labs have been updated to the latest software versions .