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Designing with Multi-Gigabit Serial I/O

Learn how to employ GTX serial transceivers in your 7 series FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.

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Designing with Multi-Gigabit Serial I/O September 8-10, 2021
$2,400.00

Title: Designing with Multi-Gigabit Serial I/O
Date/Duration: September 8-10-2021, Three
days
Times: 9 AM - 5 PM
Location:  Online

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