High-Level Synthesis with the Vitis HLS Tool
This course provides a thorough introduction to the Vitis™ High-Level Synthesis (HLS) tool. The focus of this course is on: ▪ Converting C/C++ designs into RTL implementations ▪ Learning the Vitis HLS tool flow ▪ Creating I/O interfaces for designs by using the Vitis HLS tool ▪ Applying different optimization techniques ▪ Improving throughput, area, latency, and logic by using different HLS pragmas/directives ▪ Exporting IP that can be used with the Vivado® IP catalog ▪ Downloading for in-circuit validation What's New for 2022.1 ▪ Optimizing for Throughput module: Added details on automatic array partitioning and using performance constraints to simplify loop-level pragma insertion ▪ All labs have been updated to the latest software versions
Course details with outline, daily schedule and prerequisites.
Currently Scheduled Classes
High-Level Synthesis with the Vitis HLS Tool, March 14-15th, 2022 *Confirmed to run Online
Title: High-Level Synthesis with the Vitis HLS Tool
Date/Duration: March 14-15th 2022
Times: 9- 5 PM CST daily-Confirmed to run!
Online