Course Description
This course covers all essential AMD FPGA design concepts. It affords you a solid foundation for leveraging AMD tools and technology. We cover every aspect of FPGA design, from architectural considerations to detailed timing constraints and static-timing-analysis (STA), to individual designer productivity. The comprehensive range of topics derives from combining elements of both the “FPGA Design with Vivado DS” – Level 1 & Level 2 courses, along with the “Ultra-Fast Design Methodology” course. This results in a uniquely broad range of coverage and skillsets packaged in a cost-effective time frame. That maximizes your training budget ROI. Each session is organized to reinforce learning and retention. Beyond the raw data, our certified instructors provide over-arching context and FPGA design insights.
The emphasis of this course is on:
▪ Getting started with Vivado DS
▪ Effective and compete timing constraints
▪ Key reports for analysis and debug
Level – FPGA 1 & 2
Course Details
▪ (4 sessions, 6 hr. each onsite)/30
Course Part Number – FPGA-VDES-1-2-UFDM-COMBINED
Who Should Attend? – Hardware developers who are relatively new to AMD tools and technology and who still require high level QoR, and individual productivity.
Prerequisites ▪
- Basic knowledge of the VHDL or Verilog language
- Digital design knowledge
Recommended additional training
Essential Tcl teaches the essentials of the Tcl language (and can be taken with particular focus on its application within the AMD Vivado™ Design Suite by special arrangement). It can be taken independently either before or after Vivado Adopter training as convenient (subject to availability).
Software Tools ▪ Vivado Design Suite
Skills Gained:
After completing this comprehensive training, you will have the necessary skills to:
- Create projects in Vivado DS
- Optimize synthesis and implementation
- Using graphical analysis tools within Vivado DS
- Fully and properly constrain design for STA
- Incorporate, generate and re-use IP cores
- Understand key Vivado reports for design analysis
- Insert debug cores as necessary
- Configure FPGA under different scenarios
- Describe the AMD FPGA front-to-back design flow
Structure and Content
AMD Device Architectures
- Introduction to FPGA Architecture, 3D ICs, Adaptive SoCs
Overview of FPGA architecture, SSI technology, etc.
Vivado Tool Flow
- Introduction to Vivado Project based Design Flows
Introduces the project-based flow in the Vivado Design Suite: creating a project, adding files to the project, exploring the Vivado IDE and simulating the design. - Vivado Design Suite Non-Project-based Flow
Introduces the non-project-based flow in the Vivado Design Suite: creating a design, adding source files and simulating the design.
HDL Techniques
- RTL Development
Covers basic digital coding guidelines used in an FPGA design.
Vivado Synthesis and Implementation
- Vivado Synthesis and Implementation
Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board.
Design Analysis
- Introduction to Vivado Reports
Generate Vivado timing reports to analyze failed timing paths. - Using Tcl Commands in the Vivado DS Project Flow
Explains what Tcl commands are executed in a Vivado Design Suite project flow.
Timing – Basics & Intermediate
- Introduction to Clock Constraints
Apply clock constraints and perform timing analysis. - Generated Clocks
Use the report clock networks report to determine if there are any generated clocks in a design. - I/O Constraints and Virtual Clocks
Apply I/O constraints and perform timing analysis. - Setup and Hold Violation Analysis
Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis. - Clock Group Constraints
Apply clock group constraints for asynchronous clock domains. - Introduction to Timing Exceptions
Introduces timing exception constraints and applying them to fine tune design timing. - Timing Constraints Editor
Introduces the timing constraints editor tool to create timing constraints.
Pin Planning
- Vivado Design Suite I/O Pin Planning
Use the I/O Pin Planning layout to perform pin assignments.
Power
- AMD Power Estimator Spreadsheet
Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
Design Techniques
- Synchronous Design Techniques
Introduces synchronous design techniques used in an FPGA design. - Resets
Investigates the impact of using asynchronous resets in a design.
Clocking in the UltraScale and 7-Series Architecture
- Clocking Resources
Describes various clock resources, clocking layout, and routing in a design.
Clock buffers in the UltraScale and 7-Series Architecture
- Clock Buffers
Describes all clocking buffers including MMCM, BUFG, BUGCE, etc.
I/O in the UltraScale and 7-Series Architecture
- I/O Logic Resources
Overview of I/O resources and the IOB property for timing closure.
Debugging
- HDL Instantiation Debug Probing Flow
Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer.
IP Integrator
- Designing with the IP Integrator
Use the Vivado IP integrator to create the uart_led subsystem. - Block Design Containers in the Vivado IP Integrator
Describes the block design container (BDC) feature and shows how to create a BDC in the IP integrator. - Creating and Packaging Custom IP
Create your own IP and package and include it in the Vivado IP catalog. - Using an IP Container
Use a core container file as a single file representation for an IP.
Debugging
- Introduction to the Vivado Logic Analyzer
Overview of the Vivado logic analyzer for debugging a design.
- Introduction to Triggering
Introduces the trigger capabilities of the Vivado logic analyzer.
- Debug Cores
Understand how the debug hub core is used to connect debug cores in a design.
Configuration
- Configuration Process
Reviews the FPGA configuration process, such as device power up, CRC checks, etc.Available Labs: - Vivado Design Suite Project-based Flow
- Basic Design Analysis in the Vivado IDE
- Vivado Design Rule Checks
- AMD Power Estimator Spreadsheet
- Vivado Synthesis and Implementation
- Vivado IP Flow
- Vivado Design Suite I/O Pin Planning
- Introduction to Clock Constraints
- I/O Constraints and Virtual Clocks (Featured)
- Timing Constraints Wizard
- Introduction to the Tcl Environment
- Resets
- Clocking Resources
- Creating and Packaging Custom IP
- Designing with the IP Integrator (Featured)
- Design Tool Flow
- Introduction to Timing Exceptions
- Power Analysis and Optimization Using the Vivado Design Suite
- HDL Instantiation Debug Probing Flow
- Scripting in Vivado Design Suite Project Mode
- Design Analysis Using Tcl Commands (Featured)
