Designing with AMD Verilog

After completing this comprehensive training, you will have the necessary skills to:

• Write RTL Verilog code for synthesis
• Write Verilog test fixtures for simulation
• Create a Finite State Machine (FSM) by using Verilog
• Target and optimize Xilinx FPGAs by using Verilog
• Use enhanced Verilog file I/O capability
• Run a timing simulation by using Xilinx Simprim libraries
• Create and manage designs within the Vivado Design Suite environment
• Download to the evaluation demo board

Course Outline

Day 1

Introduction to Verilog
Discusses the history of the Verilog language and provides an overview of the different features of Verilog. {Lecture}
▪ Verilog Keywords and Identifiers
Discusses the data objects that are available in the Verilog language as well as keywords and identifiers. {Lecture}
▪ Verilog Data Values and Number Representation
Covers what data values are in Verilog, as well as how to represent numbers in Verilog. {Lecture}
▪ Verilog Data Types
Covers the various data types in Verilog. {Lecture}
▪ Verilog Buses and Arrays
Covers buses and arrays in Verilog. {Lecture}
▪ Verilog Modules and Ports
Describes both the syntax and hierarchy for a Verilog module, port declarations, and the difference between reg versus wire. {Lecture, Demo, Lab}
▪ Verilog Operators
Shows the syntax for all Verilog operators. {Lecture}
▪ Continuous Assignment
Introduces the Verilog continuous assignment statement.{Lecture}
▪ Gate-Level Modeling
Introduces gate-level modeling in Verilog {Lecture}
▪ Procedural Assignment
Provides an introduction to procedural assignments in Verilog, including their usage and restrictions. {Lecture}
▪ Blocking and Non-Blocking Procedural Assignment
Introduces blocking and non-blocking assignment statements in Verilog. {Lecture, Lab}
▪ Procedural Timing Control
Introduces the timing control methods that are used in procedural assignments. {Lecture}

Day 2

Verilog Conditional Statements: if_else
Describes the if/else conditional statement. {Lecture, Lab}
▪ Verilog Conditional Statements: case
Describes the case conditional statement. {Lecture}
▪ Verilog Loop Statements
Introduces the different types of Verilog loop statements. {Lecture}
▪ Introduction to the Verilog Testbench
Introduces the concept of the Verilog testbench {Lecture, Lab}
▪ System Tasks
Provides a basic understanding of system tasks. {Lecture}
▪ Verilog Subprograms
Covers the use of subprograms in verification and RTL code to model functional blocks. {Lecture}
▪ Verilog Functions
Describes functions, which are integral to reusable and maintainable code. {Lecture}
▪ Verilog Tasks
Covers tasks in Verilog. {Lecture}
▪ Verilog Compiler Directives
Describes Verilog compiler directives. {Lecture}
▪ Verilog Parameters
Covers Verilog parameters and the local parameter concept. {Lecture, Lab}
▪ Verilog Generate Statement
Introduces the Verilog generate statement. {Lecture}

Day 3

▪ Verilog Timing Checks
Covers the timing check statements in Verilog and talks about the specify block. {Lecture}
▪ Finite State Machines
Provides an overview of finite state machines, one of the more commonly used circuits. {Lecture}
▪ Mealy Finite State Machine
Describes the Mealy FSM and how to code for it. {Lecture, Lab}
▪ Moore Finite State Machine
Describes the Moore FSM and how to code for it. {Lecture, Lab}
▪ FSM Coding Guidelines
Shows how to model an FSM of any complexity in Verilog and describes recommendations for performance and reliability. {Lecture}
▪ Avoiding Race Conditions in Verilog
Describe what a race condition is and provides steps to avoid this condition. {Lecture}
▪ File I/O: Introduction
Covers using basic and enhanced Verilog file I/O capabilities for more robust design verification. {Lecture}
▪ File I/O: Read Functions
Covers Verilog file I/O read capabilities. {Lecture, Lab}
▪ File I/O: Write Functions
Covers Verilog file I/O write capabilities. {Lecture}
▪ Targeting Xilinx FPGAs
Focuses on Xilinx-specific implementation and chip-level optimization. {Lecture, Lab}
▪ User-Defined Primitives
Describes user-defined primitives (UDPs). {Lecture}
▪ Programming Language Interface
Introduces the programming language interface (PLI) in Verilog. {Lecture}

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