Course Description
Use different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn
how to apply application partitioning, design closure, power, and thermal solutions to enhance the performance of a design.
The emphasis of this course is on:
▪ Demonstrating the embedded software development flow for Versal devices
▪ Using the provided design tools and Versal adaptive SoC design methodologies to create complex systems
▪ Leveraging the Power Design Manager (PDM) tool for power estimation
▪ Identifying Versal adaptive SoC power and thermal solutions
▪ Applying common timing closure techniques
▪ Performing system-level simulation and debugging
▪ Improving Versal adaptive SoC system performance
Level – ACAP 2
Course Details
▪ 2 days ILT/19
Course Part Number – ACAP-VDM
Who Should Attend? – Software and hardware developers, system architects, and anyone who wants to learn about the Versal adaptive SoC design methodologies
Prerequisites
▪ Basic knowledge of AMD FPGAs and adaptive SoCs
▪ Basic knowledge of the Vivado™ and Vitis™ Tools
Software Tools
▪ Vivado™ Design Suite 2024.1
▪ Vitis™ unified software platform 2024.1
▪ PetaLinux Tools 2024.1
Hardware
▪ Architecture: Versal adaptive SoC
▪ Demo board: Versal VCK190 Evaluation Platform
After completing this comprehensive training, you will have the necessary skills to:
▪ Describe the embedded software development flow for AMD Versal devices
▪ Use the provided design tools and Versal adaptive SoC design methodologies to create complex systems
▪ Leverage the Power Design Manager (PDM) tool for power estimation for Versal devices Identify Versal adaptive SoC power and thermal solutions
▪ Create a custom AMD Vitis platform to run acceleration applications
▪ Identify and apply common timing closure techniques
▪ Describe the different debugging options available for the Versal adaptive SoC
▪ Perform system-level simulation and debugging
Course Outline
Day 1
▪ Board System Design Methodology
Describes PCB, power, clocking, and I/O considerations when designing a system. {Lecture}
▪ Embedded Software Development
Describes the software development environments and embedded software development flows for Versal devices. Also
introduces embedded software debugging. {Lecture, Lab}
▪ Software Build Flow
Provides an overview of the different build flows, such as the do-it-yourself, Yocto Project, and PetaLinux tool flows. {Lecture, Lab}
▪ Software Stack
Reviews the Versal device bare-metal, FreeRTOS, and Linux software stack and their components. {Lecture}
▪ Security Management and Safety Features
Describes the security management and safety features of the Versal devices. {Lecture}
▪ System and Solution Planning Methodology
Describes design partitioning, power, and thermal guidelines. Also reviews system debug, verification, and validation planning.
{Lecture}
▪ Application Partitioning 1
Covers what application partitioning is and how the mapping of resources based on the models of computation can be performed.
{Lecture}
▪ Power Design Manager
Discusses using the new Power Design Manager tool, including import and export functions. {Lecture, Lab}
Day 2
▪ Power and Thermal Solutions
Discusses the power domains in the Versal adaptive SoC as well as power optimization and analysis techniques. Thermal design
challenges are also covered. {Lecture}
▪ Hardware, IP, and Platform Development Methodology
Describes the different Versal device design flows and covers the custom platform creation process using the Vivado IP integrator,
RTL, HLS, and Vitis environment. {Lecture, Lab}
▪ Timing Closure Overview
Describes the timing closure and baselining of a design. Also explains QoR reports and timing violation analysis. {Lecture}
▪ Timing Closure Techniques
Lists the common timing closure techniques for logic optimization, design analysis, and timing closure. Also describes the timing
considerations for SSI technology devices. {Lecture}
▪ System Integration and Validation Methodology
Describes different simulation flows as well as timing and power closure techniques. Also explains how to improve system
performance. {Lecture}
▪ Configuration and Debugging
Describes the configuration and debug process for the Versal devices. Also covers the Versal device debug interfaces, such as
the test access port (TAP) and debug access port (DAP) controller. {Lecture}
▪ Overview of HSDP
Describes the high-speed debug port (HSDP) in the Versal device. Also goes over the steps to use the SmartLynq+ module
for high-speed debugging. {Lecture, Lab}
▪ Fabric Debug
Explains the fabric debug features available in the Versal devices and reviews the different debug IP cores supported for the Versal
devices, such as the AXI Debug Hub, AXIS ILA, and AXIS VIO. {Lecture, Lab}
▪ System Simulation
Explains how to perform system-level simulation in a Versal device design. {Lecture, Lab}
PDF Version Designing with the Versal Adaptive SoC Design Methodology
