AMD DSP Design for FPGAs with MATLAB and AMD Vitis HLS

** Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations. The ZCU104 board is required for the “AXI4-Lite Interface Synthesis” lab.
After completing this comprehensive training, you will have the necessary skills to:
▪ Describe the Model Composer design flow for implementing DSP functions
▪ Identify AMD FPGA capabilities and how to implement a design from algorithm concept to hardware simulation
▪ List various low-level and high-level functional blocks available in Model Composer
▪ Run hardware co-simulation
▪ Identify the high-level blocks available for FIR and FFT designs
▪ Implement multi-rate systems in Model Composer
▪ Integrate optimized FPGA models into the Vivado IDE
▪ Design a processor-controllable interface for DSP
▪ Generate IPs from C-based design sources using the Vitis HLS tool for use in the Model Composer environment
▪ Create and simulate designs using Model Composer and HLS

Course Outline
Session 1
▪ Introduction to Model Composer
▪ Simulink Software Basics
▪ Lab 1: Using the Simulink Software
▪ HDL Library in Vitis Model Composer
▪ Lab 2: HDL Library in Vitis Model Composer
▪ HDL Library: Co-Simulation and Hardware Co-Simulation
▪ DSP Blocks in Vitis Model Composer
▪ Signal Routing
▪ Lab 3: Signal Routing
Session 2
▪ Implementing System Control
▪ Filter Design
▪ Lab 4: Designing a MAC-Based FIR
▪ Multi-Rate Systems
▪ Lab 5: Designing a FIR Filter Using the FIR Compiler Block
▪ Intro to HLS Design Flow
▪ HLS Directives/Pragmas & IP Optimization
Session 3
▪ HLS I/O Interface Optimization
▪ HLS dataflow and pipelining Optimization
▪ Lab 6: AXI4-Lite Interface Synthesis
▪ HLS Library in Vitis Model Composer
▪ Lab 7: Model Composer and Vitis HLS Tool Integration
▪ Appendix: Exploring Vitis MC Examples in Github
Appendix Labs: See manual for details
Lab Descriptions
▪ Lab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system.
Understand the effect sampling rate.
▪ Lab 2: HDL Library in Vitis Model Composer – Illustrates a DSP48-based design. Perform hardware co-simulation verification
targeting an AMD evaluation board.
▪ Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.
▪ Lab 4: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify
through hardware co-simulation by using an AMD evaluation board.
▪ Lab 5: Designing a FIR Filter Using the FIR Compiler Block –
Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through
hardware co-simulation by using an AMD evaluation board.
▪ Lab 6: AXI4-Lite Interface Synthesis – Package a System Generator for DSP design with an AXI4-Lite interface and
integrate this packaged IP into a Zynq UltraScale+ MPSoC processor system. Then create and debug the application project
using the Vitis IDE.
▪ Lab 7: System Generator and Vitis HLS Tool Integration – Generate IP from a C-based design to use with System Generator.