Designing FPGAs Using the Vivado Design Suite 2

FPGA-VDES2

Course Description

Learn how to build a more effective FPGA design:
The focus is on:
▪ Using synchronous design techniques
▪ Utilizing the Vivado® IP integrator to create a sub-system
▪ Employing proper HDL coding techniques to improve design performance
▪ Debugging a design with multiple clock domains
This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.
What's New for 2019.2
▪ UltraFast Design Methodology – Design Creation: Auto-pipelining considerations
▪ Designing with the IP Integrator: Additional description of IPI features

Level: FPGA 2

Course Duration: 2 days
Price: $1600 or 16 Xilinx Training Credits
Course Part Number: FPGA-VDES2
Who Should Attend?:Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs.
Registration: Register online in our secure store

Prerequisites

  • Designing FPGA's Using the Vivado Design Suite 1 course
  • Working HDL knowledge (VHDL or Verilog)
  • Digital design experience

Optional Videos

  • Basic HDL Coding Techniques*

Software Tools 

  • Vivado System Edition 2019.2

Hardware

  • Architecture: UltraScale™ family**
  • Demo board (optional): Zynq® UltraScale+™ MPSoC ZCU104 board**

** This course focuses on the UltraScale architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab
board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:
▪ Identify synchronous design techniques
▪ Build resets into your system for optimum reliability and design speed
▪ Create a Tcl script to create a project, add sources, and implement a design
▪ Describe and use the clock resources in a design
▪ Create and package your own IP and add to the Vivado IP catalog to reuse
▪ Use the Vivado IP integrator to create a block design
▪ Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
▪ Describe how power analysis and optimization is performed
▪ Describe the HDL instantiation flow of the Vivado logic analyzer

 Course Outline

Day 1
UltraFast Design Methodology: Design Creation
Overview of the methodology guidelines covered in this course. {Lecture}
Synchronous Design Techniques
Introduces synchronous design techniques used in an FPGA design. {Lecture}
Resets
Investigates the impact of using asynchronous resets in a design. {Lecture, Lab}
Register Duplication
Use register duplication to reduce high fanout nets in a design. {Lecture}
▪ Scripting in Vivado Design Suite Project Mode

Explains how to write Tcl commands in the project-based flow for a design. {Lecture, Lab}
▪ Clocking Resources
Describes various clock resources, clocking layout, and routing in a design. {Lectures, Lab}
▪ I/O Logic Resources
Overview of I/O resources and the IOB property for timing closure. {Lectures}
▪ Creating and Packaging Custom IP
Create your own IP and package and include it in the Vivado IP catalog. {Lecture, Lab}

Day 2

▪ Using an IP Container
Use a core container file as a single file representation for an IP. {Lecture, Demo}
▪ Designing with the IP Integrator
Use the Vivado IP integrator to create the uart_led subsystem. {Lecture, Demo, Lab, Case Study}
▪ Timing Constraints Editor
Introduces the timing constraints editor tool to create timing constraints. {Lecture}
▪ Report Clock Networks
Use report clock networks to view the primary and generated clocks in a design. {Lecture, Demo}
▪ Timing Summary Report
Use the post-implementation timing summary report to sign-off criteria for timing closure. {Lecture, Demo}
▪ Clock Group Constraints
Apply clock group constraints for asynchronous clock domains. {Lecture, Demo}
▪ Introduction to Timing Exceptions
Introduces timing exception constraints and applying them to fine tune design timing. {Lecture, Demo, Lab}
▪ Power Analysis and Optimization Using the Vivado Design Suite
Use report power commands to estimate power consumption. {Lecture, Lab}
▪ Configuration Process
Understand the FPGA configuration process, such as device power up, CRC check, etc. {Lecture}
▪ HDL Instantiation Debug Probing Flow
Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer. {Lecture, Lab}
▪ Design Analysis Using Tcl Commands
Analyze a design using Tcl commands. {Lecture, Demo, Lab}

 PDF version of this page.

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Scheduled FPGA Courses

Private Onsite
July 08 - July 09: 09:00 am - 05:00 pm
* v2016.1 This course provides a through introduction to the Vivado High-Level Synthesis (HLS)...

Private onsite
July 28 - July 31: 09:00 am - 05:00 pm
Custom On-Site Training is available when public Xilinx instructor-led courses do not meet...

Private Onsite
August 05 - August 07: 09:00 am - 05:00 pm
* v2016.1 This course provides a through introduction to the Vivado High-Level Synthesis (HLS)...

Private onsite
August 10 - August 11: 09:00 am - 05:00 pm
Custom On-Site Training is available when public Xilinx instructor-led courses do not meet...

C-Based Design: High-Level synthesis with the Vivado HLx Tool
October 08 - October 09: 09:00 am - 05:00 pm
v2018.2 This course provides a through introduction to the Vivado High-Level Synthesis (HLS) tool....

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.