Designing with Versal AI Engine 1: Architecture and Design Flow

ACAP-AIE1

Course Description

 

Level: ACAP 2
Course Duration: 2 days
Price: $1600 or 16 Xilinx Training Credits
Course Part Number: AI-INFER
Who Should Attend?: – Software and hardware developers, system architects, and anyone wo needs to accelerate their software applications using Xilinx devices.


Registration: Register online in our secure store

Prerequisites
▪ Comfort with the C/C++ programming language
▪ Software development flow
▪ Vitis software for application acceleration development flow Software Tools
▪ Vitis unified software platform 2021.1 Hardware
▪ Architecture: Xilinx Versal ACAPs

After completing this comprehensive training, you will have the
necessary skills to:
▪ Describe the Versal ACAP architecture at a high level
▪ Describe the various engines in the Versal ACP device and the motivation behind the AI Engine
▪ Describe the architecture of the AI Engine
▪ Describe the memory access structure for the AI Engine
▪ Describe the full application acceleration flow with the Vitis tool
▪ Enumerate the toolchain for Versal AI Engine programming
▪ Explain what intrinsic functions are
▪ Program a single AI Engine kernel using the XChessDE tool
▪ Program multiple AI Engine kernels using static data flow (SDF) graphs

Course Outline 2021.2

Day 1
▪ Overview of Versal ACAP Architecture
Provides an overview of the Versal architecture at a high level and describes the various engines in the Versal ACAP, such as the Scalar Engines, Adaptable Engines, and Intelligent Engines.
Also describes how the AI Engine in the Versal ACAP meets many dynamic market needs. {Lecture}
Introduction to the Versal AI Engine Architecture
Introduces the architecture of the AI Engine and describes the AI Engine interfaces that are available, including the memory, lock, core debug, cascaded stream, and AXI-Stream interfaces.
{Lecture}
▪ Versal AI Engine Memory and Data Movement
Describes the memory module architecture for the AI Engine and how memory can be accessed by the AI Engines in the AI Engine
arrays. {Lecture}
Versal AI Engine Tool Flow
Reviews the Vitis tool flow for the AI Engine and demonstrates the full application acceleration flow for the Vitis platform. Also ntroduces the XChessDE tool.{Lecture, Lab}
Application Partitioning on Versal ACAPs
Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal ACAP. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal ACAP. {Lecture}
Data Types: Scalar and Vector Data Types
Provides an AI Engine functional overview and identifies the supported vector data types and high-width registers for allowing single-instruction multiple-data (SIMD) instructions. {Lecture}
Intrinsic Functions
Describes what intrinsic functions are, the three types of vector management operations using intrinsic functions (load and store, element conversion, and lane insertion/extraction), multiplication functions, and application-specific functions. {Lecture}

Day 2


▪ Window and Streaming Data APIs
Describes window and streaming APIs and reviews the various window operations for kernels. Also discusses using overlapping data and various data movement use cases. {Lecture}
The Programming Model: Single Kernel
Reviews the AI Engine kernel programming flow for programming and building a single kernel. Also illustrates the steps to create, compile, simulate, and debug a single kernel program using the
XChessDE tool. {Lecture, Lab}
▪ The Programming Model: Introduction to the Data Flow Graph
Provides the basics of the data flow graph model and graph input
specifications for AI Engine programming. Also reviews graph input specifications, such as the number of platforms and ports. {Lecture}
The Programming Model: Multiple Kernels Using Graphs
Describes the static data flow (SDF) graph and demonstrates the steps to create a graph and set the runtime ratio and graph control APIs from the main application program. {Lecture, Lab}

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Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.