Zynq UltraScale+MPSoC-Hardware Designer

Zynq UltraScale+MPSoC-Hardware Designer

Course Part Number-EMBD-ZUPHW

Course Description


This course provides hardware designers with an overview of the
capabilities and support for the Zynq® UltraScale+™ MPSoC family
from a hardware architectural perspective.
The emphasis is on:
▪ Identifying the key elements of the application processing unit
(APU) and real-time processing unit (RPU)
▪ Reviewing the various power domains and their control structure
▪ Illustrating the processing system (PS) and programmable logic
(PL) connectivity
▪ Utilizing QEMU to emulate hardware behavior

Level: Embedded Software 3 

Course Duration: 2 days 

Price: $1600 or 16 Xilinx Training Credits
Course Part Number: EMBDZUPHW-ILT 
Who Should Attend?: Hardware developers interested in understanding the Zynq UltraScale+ MPSoC device.


Registration: Register online in our secure store

Prerequisites

  • Suggested: Understanding of the Zynq-7000 architecture
  • Basic familiarity with embedded software development using C (to support testing of specific architectural elements)

Software Tools

  •  Vivado Design Suite 2020.1
  • May require special Zynq UltraScale+MPSoC family license

Hardware

  • VirtualBox
  • QEMU
  • Ubantu desktop
  • PetaLinux
  • Zynq UltraScale+ MPSoC ZCU104 board*

 Contact us for the specifics of the in-class lab board or other customizations.


* This course focuses on the Zynq UltraScale+ MPSoC architecture.
Check with your local Authorized Training Provider for the specifics of
the in-class lab environment or other customizations. This version of
the class does not use a physical board, but rather a local emulation
environment and the Vivado Design Suite

After completing this comprehensive training , you will have the necessary skills to:

  • Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
  • List the various power domains and how they are controlled
  • Describe the connectivity between the processing system (PS) and programmable logic(PL)
  • Utilize QEMU to emulate hardware behavior

Course Outline

Day 1

▪ Application Processing Unit
Introduction to the members of the APU, specifically the
Cortex™-A53 processor and how the cluster is configured and
managed. {Lectures, Lab}
▪ HW-SW Virtualization
Covers the hardware and software elements of virtualization. The
lab demonstrates how hypervisors can be used. {Lectures, Demo,
Lab}
Real-Time Processing Unit
Focuses on the real-time processing module (RPU) in the PS,
which is comprised of a pair of Cortex processors and supporting
elements.. {Lectures, Demo, Lab}
QEMU
Introduction to the Quick Emulator, which is the tool used to run
software for the Zynq UltraScale+ MPSoC device when hardware
is not available. {Lectures, Demos}
▪ Booting
How to implement the embedded system, including the boot
process and boot image creation. {Lectures, Lab}
▪ First Stage Boot Loader
Demonstrates the process of developing, customizing, and
debugging this mandatory piece of code. {Lecture, Demo}


Day 2

  Video
Introduction to video, video codecs, and the Video Codec Unit
available in the Zynq UltraScale MPSoC. {Lectures}
▪ System Protection
Covers all the hardware elements that support the separation of
software domains. {Lectures}
▪ Clocks and Resets
Overview of clocking and reset, focusing more on capabilities
than specific implementations. {Lectures, Demos}
▪ AXI
Understanding how the PS and PL connect enables designers to
create more efficient systems. {Lectures, Demo, Lab}
▪ Power Management
Overview of the PMU and the power-saving features of the device {Lecture. Lab}

 

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Scheduled Embedded Courses

Designing FPGAs Using the Vivado Design Suite 1
October 01 - October 02: 09:00 am - 05:00 pm
This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

Migrating to Vitis Embedded Software Development IDE
October 07 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to:▪ Develop and...

Zynq UltraScale+ MPSoC
October 20 - October 22: 09:00 am - 05:00 pm
This course provides an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC...

Embedded Design with PetaLinux Tools
October 27 - October 28: 09:00 am - 05:00 pm
Provides embedded systems developers with experience in creating an embedded Linux system targeting...

Designing FPGAs Using the Vivado Design Suite 2
November 09 - November 10: 09:00 am - 05:00 pm
This course shows you how to build an effective FPGA design using synchronous design techniques,...

Accelerating Applications with the Vitis Unified Software Environment
November 12 - November 13: 09:00 am - 05:00 pm
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™...

(Workshop) Embedded & Accelerating Applications w/Vitis Unified Software
November 16 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to: ▪ Implement...

Zynq UltraScale+ MPSoC
December 01 - December 03: 09:00 am - 05:00 pm
This course provides an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC...

Designing FPGAs Using the Vivado Design Suite 3
December 07 - December 08: 09:00 am - 05:00 pm
This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

Zynq SoC System Architecture
December 09 - December 10: 09:00 am - 05:00 pm
* This course focuses on the Zynq-7000 SoC. Check with your local Authorized Training Provider for...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.