DSP Design Using System Generator

DSP-SYSGEN-ILT

Course Description

Explore the System Generator tool and gain the expertise needed to develop advanced, low-cost DSP designs.
This course focuses on:
▪ Implementing DSP functions using System Generator for DSP
▪ Utilizing design implementation tools
▪ Verifying through hardware co-simulation
What's New for 2019.2
▪ Introduction to Model Composer: New block descriptions
▪ Automatic Code Generation: Additional Model Composer
information

Level: DSP 3
Course Duration: 2 days
Price: $1600 or 16 Xilinx Training Credits
Course Part Number: DSP-SYSGEN-ILT 

Who Should Attend?: – – System engineers, system designers, logic
designers, and experienced hardware engineers who are implementing
DSP algorithms using the MathWorks MATLAB® and Simulink®
software and want to use Xilinx System Generator for DSP design

Prerequisites

▪ Experience with the MATLAB and Simulink software
▪ Basic understanding of sampling theory
Software Tools
▪ Vivado® Design Suite System Edition 2019.2
▪ Model Composer
▪ MATLAB with Simulink software R2018a, R2018b, R2019a, R2019b
Hardware
▪ Architecture: 7 series and UltraScale™ FPGAs
▪ Demo board: Kintex®-7 FPGA KC705 board or Kintex UltraScale™
FPGA KCU105 board and Zynq® UltraScale+™ MPSoC ZCU104 board*

* Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations. The ZC702 or ZedBoard is required for the "AXI4-Lite Interface Synthesis" lab. 

After completing this comprehensive training, you will have the necessary skills to:

 

  • Describe the System Generator design flow for implementing  DSP functions
  • Identify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulation 
  • List various low-level and high-level functional blocks available in System Generator 
  • Run hardware co-simulation 
  • Identify the high-level blocks available for FIR and FFT designs 
  • Implement multi-rate systems in System Generator 
  • Integrate System Generator models into the Vivado IDE 
  • Design a processor-controllable interface using System Generator for DSP 
  • Generate IPs from C-based design sources for use in the System Generator environment 

 

Course Outline

Day 1

 

  • Introduction to System Generator 
  • Simulink Software Basics 
  • Lab 1: Using the Simulink Software 
  • Basic Xilinx Design Capture 
  • Demo: System Generator Gateway Blocks 
  • Lab 2: Getting Started with Xilinx System Generator 
  • Signal Routing 
  • Lab 3: Signal Routing 
  • Implementing System Control 
  • Lab 4: Implementing System Control 

 

Day 2

 

  • Multi-Rate Systems 
  • Lab 5: Designing a MAC-Based FIR 
  • Filter Design 
  • Lab 6: Designing a FIR Filter Using the FIR Compiler Block 
  • System Generator, Vivado Design Suite, and Vivado HLS Integration 
  • Lab 7: System Generator and Vivado IDE Integration 
  • Kintex-7 FPGA DSP Platforms 
  • Lab 8: System Generator and Vivado HLS Tool Integration 
  • Lab 9: AXI4-Lite Interface Synthesis 
  • Introduction to Model Composer

 

 Lab Descriptions

 

  • Lab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.
  •  Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board. 
  • Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks. 
  • Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode. 
  • Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board. 
  • Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.
  • Lab 7: System Generator and Vivado IDE Integration – Embed System Generator models into the Vivado IDE.
  • Lab 8: System Generator and Vivado HLS Tool Integration – Generate IP from a C-based design to use with System Generator. 
  • Lab 9: AXI4-Lite Interface Synthesis – Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq All Programmable SoC processor system.
  • Lab 10: Model Composer and Vivado IDE Integration - Embed a Model Composer model into the Vivado IDE.

PDF version of this page.

Enroll Now.

Scheduled DSP Courses

Designing with the Zynq UltraScale+ RFSoC 3
October 06 - October 08: 09:00 am - 05:00 pm
This course provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC...

Designing with the Zynq UltraScale+ RFSoC 3
November 17 - November 19: 09:00 am - 05:00 pm
This course provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC...

Designing with the Zynq UltraScale+ RFSoC 3
December 15 - December 17: 09:00 am - 05:00 pm
This course provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.