UltraFast Design Metholology

  • UltraFast Design Methodology

FPGA-VDM

Course Description

  • Learn how to improve design speed and reliability by using the UltraFast Design Methodology and the Vivado® Design Suite.
    The focus is on:
    ▪ Optimizing system reset design and synchronization circuits
    ▪ Employing best practice HDL coding techniques
    ▪ Applying appropriate timing closure techniques
    ▪ Reviewing an UltraFast Design Methodology case study
    What's New for 2021.2
    UltraFast Design Methodology: Introduction: Adds overview of the
    Versal architecture; also provided different available resources for
    learning the Versal ACAP design methodology
    ▪ UltraFast Design Methodology: Board and Device Planning: Adds
    information about power constraints
    ▪ Designing with the IP Integrator: Adds description about block
    design containers in the Vivado IP integrator
    ▪ All labs have been updated to the latest software versions

 

Level: FPGA 3 
Course Duration: 2 day
Price: $1600 or 16 Xilinx Training Credits
Course Part Number: FPGA-VDM
Who Should Attend?:Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.
Registration: Register online in our secure store

Prerequisites

  • Basic HDL knowledge (VHDL or Verilog)
    Digital design knowledge and experience

Software Tools

  • Vivado Design or System Edition 2021.2

Hardware

  • Architecture: UltraScale TM FPGAs*
  • Demo board: None

 * This course focuses on the UltraScale architecture. Check with your local Authorized Training Provider for specifics or other customizations.
After completing this comprehensive training, you will have the necessary skills to:
▪ Describe the UltraFast™ design methodology checklist
▪ Identify key areas to optimize your design to meet your design goals and performance objectives
▪ Define a properly constrained design
▪ Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
▪ Build resets into your system for optimum reliability and design speed
▪ Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
▪ Identify timing closure techniques using the Vivado Design Suite
▪ Describe how the UltraFast design methodology techniques work effectively through case studies and lab experience

PDF Course Outline

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Scheduled FPGA Courses

*Confirmed to run! Designing FPGAs Using Vivado Design Suite 4
July 11 - July 12: 09:00 am - 05:00 pm
This course tackles the most sophisticated aspects of the Vivado Design Suite and Xilinx hardware....

Designing with the UltraScale & US+ Architecture
July 28 - July 29: 09:00 am - 05:00 pm
This course introduces the UltraScale™ and UltraScale+™architectures to both new and experienced...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.