• UltraFast Design Methodology

FPGA-VDM

Course Description

• Learn how to improve design speed and reliability by using the UltraFast Design Methodology and the Vivado® Design Suite.
  The focus is on:
  ▪ Optimizing system reset design and synchronization circuits
  ▪ Employing best practice HDL coding techniques
  ▪ Applying appropriate timing closure techniques
  ▪ Reviewing an UltraFast Design Methodology case study
  What's New for 2021.2
  UltraFast Design Methodology: Introduction: Adds overview of the
  Versal architecture; also provided different available resources for
  learning the Versal ACAP design methodology
  ▪ UltraFast Design Methodology: Board and Device Planning: Adds
  information about power constraints
  ▪ Designing with the IP Integrator: Adds description about block
  design containers in the Vivado IP integrator
  ▪ All labs have been updated to the latest software versions

Level: FPGA 3 
Course Duration: 2 day
Price: $1600 or 16 Xilinx Training Credits
Course Part Number: FPGA-VDM
Who Should Attend?:Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.
Registration: Register online in our secure store

Prerequisites

• Basic HDL knowledge (VHDL or Verilog)
  Digital design knowledge and experience

Software Tools

• Vivado Design or System Edition 2021.2

Hardware

• Architecture: UltraScale TM FPGAs*
• Demo board: None