Timing Closure Techniques

FPGA ADVTIMING

Course Description

Course Details

  • 2 Day $1600 or 16 Training Credits
  • 11 lectures
  • 6 labs

Who Should Attend? – Software and hardware developers, system architects, and anyone who wants to learn about UltraFast Design Methodology timing closure techniques
Prerequisites
▪ Basic knowledge of FPGA and SoC architecture and HDL coding techniques
▪ Basic knowledge of the Vivado® Design Suite
Software Tools
▪ Vivado Design Suite 2021.2
Hardware
▪ Architecture: UltraScale™ FPGAs and Versal® ACAPs

After completing this comprehensive training, you will have the
necessary skills to:
▪ Describe UltraFast Design Methodology timing closure techniques
▪ Resolve setup and hold violations
▪ Reduce logic delay and net delay
▪ Reduce congestion
▪ Improve clock skew and clock uncertainty
▪ Perform Pblock-based and SLR-based analysis
▪ Identify clock domain crossings (CDC) and scenarios that require synchronization circuits
▪ Perform QoR assessment at different stages and improve the QoR score
▪ Implement Intelligent Design Runs (IDR)

Course Outline

Day 1
Static Timing Analysis
▪ Introduction to Clocking and Static Timing Analysis (STA)
 Describes the basics of clock gating, static timing analysis, and
 setup and hold slack. {Lecture}
UltraFast Design Methodology Timing Closure
▪ Introduction to UltraFast Design Methodology Timing Closure
 Provides an overview of the various stages of the UltraFast
 Design Methodology for timing closure. {Lecture}
Baselining
▪ Baselining
Demonstrates the performance baselining process, which is an iterative approach to incrementally constrain a design and meet timing. {Lecture, Lab}
Design Analysis and Optimization
▪ Setup and Hold Violation Analysis
Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis. {Lecture}
▪ Reducing Logic Delay
Describes how to optimize regular fabric paths and paths with dedicated blocks and macro primitives. {Lecture}
▪ Reducing Net Delay
Reviews different techniques to reduce congestion and net delay.
{Lecture, Lab}

Day 2

Design Analysis and Optimization (Continue)
▪ Improving Clock Skew
Describes how to apply various techniques to improve clock
skew. {Lecture}
▪ Improving Clock Uncertainty
Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing
CDC) paths. {Lecture, Lab}
Clock Domain Crossing (CDC)
▪ Clock Domain Crossing (CDC) and Synchronization Circuits
Explains what clock domain crossings (CDC) are and the scenarios that require synchronization circuits. {Lecture, Lab}
Report QoR
▪ QoR Reports Overview
Describes what quality of result (QoR) is and how to analyze the
QoR reports generated by the Vivado IDE. {Lecture, Lab}
Design Runs
▪ Intelligent Design Runs (IDR)
Introduces Intelligent Design Runs (IDR), which are special types
of implementation runs that use a complex flow to attempt to close timing. {Lecture, Lab}

PDF Version

Scheduled Embedded Courses

Free Workshop! Migrating from ISE & Spartan 6 to Vivado & 7 Series
June 03 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have the necessary skills to: ▪ Analyze...

*FREE Workshop! Using Vision-based App w/ the Kria KV260 Vision AI Starter Kit & SOM
June 06 - June 07: 10:30 am - 04:00 pm
After completing this comprehensive training, you will have the necessary skills to: ▪ Describe the...

Zynq UltraScale+ MPSoC *Confirmed to run!
June 06 - June 09: 11:00 am - 05:00 pm
Course DescriptionThis course provides an overview of the capabilities and support for the Zynq®...

Designing FPGAs Using the Vivado Design Suite 3
June 09 - June 10: 09:00 am - 05:00 pm
 This course demonstrated timing closure techniques, such are baselining,...

Designing with the IP Integrator Tool
June 17 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have the necessary skills to:▪ Describe the...

Accelerating Applications with the Vitis Unified Software Environment
June 20 - June 22: 09:00 am - 05:00 pm
After completing this comprehensive training, you will have the necessary skills to:▪ Describe how...

Designing with Versal AI Engine 2:Graph Programming w/AI Engine Kernels
July 07 - July 08: 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to:▪ Describe the...

Zynq UltraScale+ MPSoC
July 11 - July 14: 11:00 am - 05:00 pm
EMBDZUPMPSoC Course DescriptionThis course provides an overview of the capabilities and support...

Designing w/the Xilinx Serial Transceivers
July 14 - July 15: 09:00 am - 05:00 pm
Learn how to employ serial transceivers in UltraScale™ and UltraScale+™ FPGA designs or Zynq®...

Designing with the Versal ACAP: PCI Express System
July 25 - July 26: 09:00 am - 05:00 pm
Course OutlineDay 1 ▪ Introduction to PCI ExpressIntroduces the course and discusses a few key...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.