Introduction to the Zynq SoC Architecture

INTRO-ZARCH

Course Description

This course provides hardware and firmware engineers with the knowledge to effectively utilize a Zynq® System on a Chip (SoC). It covers the architecture of the ARM® Cortex™-A9 processor-based processing system (PS) and the integration of programmable logic (PL). The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL. 

Level: Embedded Hardware and Firmware 3
Course Duration: 1 day
Price: $800 or 8 Xilinx Training Credits
Course Part Number: INTRO-ZARCH
Who Should Attend?: Hardware and firmware engineers who are interested in implementing a system on a chip using the Zynq SoC and programmable logic.
Registration: Register online in our secure store

Prerequisites

  • FPGA design experience
  • Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx ISE® software implementation tools
  • Basic understanding of C programming
  • Basic understanding of microprocessors
  • Some HDL modeling experience

Software Tools

  • Xilinx® Design Suite: Embedded or System Edition 2018.1

Hardware

  • Architecture: Zynq-7000 SoC*
  • Demo board: Zynq-7000 SoC ZC702 or Zed board*

* This course focuses on the Zynq-7000 SoC. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the architecture and components that comprise the Zynq SoC processing system (PS)
  • Evaluate a processing system (PS) and programmable logic (PL) AXI interface
  • Identify the configuration options for the Zynq SoC

Course Outline

  • Overview {Lecture, Demo}
  • Application Processor Unit (APU) {Lecture, Lab}
  • Processor Input/Output Peripherals {Lecture, Demo}
  • PS-PL Interface {Lecture, Demo, Lab}
  • Booting {Lecture, Lab}
  • Memory Resources {Lecture, Demo}

Topic Descriptions

  • Overview – Provides a general overview of the Zynq SoC.
  • Application Processor Unit (APU) – Explores the individual
    components that comprise the APU.
  • Processor Input/Output Peripherals – Introduces the components
    that comprise the IOP block of the Zynq device PS.
  • PS-PL Interface – Describes in detail the PS interconnect and
    how it affects PL architecture decisions.
  • Booting – Explains the boot process of the PC and configuration
    of the PL.
  • Memory Resources – Explains the operation of the on-chip
    (OCM) memory and various memory controllers located in the PS

 PDF version of this page.

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Scheduled Embedded Courses

Zynq UltraScale+MPSoC-Software Developer
March 03 - March 04: 09:00 am - 05:00 pm
v2016.3 This two-day course is structured to provide software designers with a catalog of OS...

Zynq UltraScale+MPSoC-System Architect
March 05 - March 06: 09:00 am - 05:00 pm
This two-day online course is structured to provide system architects with an overview of the...

(Workshop) Embedded & Accelerating Applications w/Vitis Unified Software
March 16 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to: ▪ Implement...

Designing FPGAs Using the Vivado Design Suite 3
March 17 - March 18: 09:00 am - 05:00 pm
This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

(Workshop) Embedded & Accelerating Applications w/Vitis Unified Software
March 24 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to: ▪ Implement...

Zynq UltraScale+MPSoC-Software Developer-Online
April 09 - April 10: 09:00 am - 05:00 pm
This two-day course is structured to provide software designers with a catalog of OS implementation...

Designing FPGAs Using the Vivado Design Suite 3
April 16 - April 17: 09:00 am - 05:00 pm
This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

Accelerating Applications with the Vitis Unified Software Environment
April 23 - April 24: 09:00 am - 05:00 pm
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™...

Accelerating Applications with the Vitis Unified Software Environment
April 28 - April 29: 09:00 am - 05:00 pm
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™...

Zynq UltraScale+MPSoC-Software Developer
April 30 - May 01: 09:00 am - 05:00 pm
This two-day course is structured to provide software designers with a catalog of OS implementation...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.