Introduction to the Zynq SoC Architecture

INTRO-ZARCH

Course Description

This course provides hardware and firmware engineers with the knowledge to effectively utilize a Zynq® System on a Chip (SoC). It covers the architecture of the ARM® Cortex™-A9 processor-based processing system (PS) and the integration of programmable logic (PL). The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL. 

Level: Embedded Hardware and Firmware 3
Course Duration: 1 day
Price: $800 or 8 Xilinx Training Credits
Course Part Number: INTRO-ZARCH
Who Should Attend?: Hardware and firmware engineers who are interested in implementing a system on a chip using the Zynq SoC and programmable logic.
Registration: Register online in our secure store

Prerequisites

  • FPGA design experience
  • Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx ISE® software implementation tools
  • Basic understanding of C programming
  • Basic understanding of microprocessors
  • Some HDL modeling experience

Software Tools

  • Xilinx® Design Suite: Embedded or System Edition 2018.1

Hardware

  • Architecture: Zynq-7000 SoC*
  • Demo board: Zynq-7000 SoC ZC702 or Zed board*

* This course focuses on the Zynq-7000 SoC. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the architecture and components that comprise the Zynq SoC processing system (PS)
  • Evaluate a processing system (PS) and programmable logic (PL) AXI interface
  • Identify the configuration options for the Zynq SoC

Course Outline

  • Overview {Lecture, Demo}
  • Application Processor Unit (APU) {Lecture, Lab}
  • Processor Input/Output Peripherals {Lecture, Demo}
  • PS-PL Interface {Lecture, Demo, Lab}
  • Booting {Lecture, Lab}
  • Memory Resources {Lecture, Demo}

Topic Descriptions

  • Overview – Provides a general overview of the Zynq SoC.
  • Application Processor Unit (APU) – Explores the individual
    components that comprise the APU.
  • Processor Input/Output Peripherals – Introduces the components
    that comprise the IOP block of the Zynq device PS.
  • PS-PL Interface – Describes in detail the PS interconnect and
    how it affects PL architecture decisions.
  • Booting – Explains the boot process of the PC and configuration
    of the PL.
  • Memory Resources – Explains the operation of the on-chip
    (OCM) memory and various memory controllers located in the PS

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Scheduled Embedded Courses

Free Workshop! Migrating from ISE & Spartan 6 to Vivado & 7 Series
June 03 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have the necessary skills to: ▪ Analyze...

*FREE Workshop! Using Vision-based App w/ the Kria KV260 Vision AI Starter Kit & SOM
June 06 - June 07: 10:30 am - 04:00 pm
After completing this comprehensive training, you will have the necessary skills to: ▪ Describe the...

Zynq UltraScale+ MPSoC *Confirmed to run!
June 06 - June 09: 11:00 am - 05:00 pm
Course DescriptionThis course provides an overview of the capabilities and support for the Zynq®...

Designing FPGAs Using the Vivado Design Suite 3
June 09 - June 10: 09:00 am - 05:00 pm
 This course demonstrated timing closure techniques, such are baselining,...

Designing with the IP Integrator Tool
June 17 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have the necessary skills to:▪ Describe the...

Accelerating Applications with the Vitis Unified Software Environment
June 20 - June 22: 09:00 am - 05:00 pm
After completing this comprehensive training, you will have the necessary skills to:▪ Describe how...

Designing with Versal AI Engine 2:Graph Programming w/AI Engine Kernels
July 07 - July 08: 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to:▪ Describe the...

Zynq UltraScale+ MPSoC
July 11 - July 14: 11:00 am - 05:00 pm
EMBDZUPMPSoC Course DescriptionThis course provides an overview of the capabilities and support...

Designing w/the Xilinx Serial Transceivers
July 14 - July 15: 09:00 am - 05:00 pm
Learn how to employ serial transceivers in UltraScale™ and UltraScale+™ FPGA designs or Zynq®...

Designing with the Versal ACAP: PCI Express System
July 25 - July 26: 09:00 am - 05:00 pm
Course OutlineDay 1 ▪ Introduction to PCI ExpressIntroduces the course and discusses a few key...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.