Essentials of Xilinx FPGA Design Course

FPGA 2 | FPGA13000-14-ILT (v1.0)

Course Description

Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.

This course covers ISE software features such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints.

For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.

Level: FPGA 2
Course Duration: 1 day
Price: $800 or 8 Xilinx Training Credits
Course Part Number: FPGA13000-ILT
Who Should Attend?: Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Optional Videos


  • Working HDL knowledge (VHDL or Verilog)
  • Digital design experience

Software Tools

  • Vivado Design or System Edition 2014.7


  • Architecture: 7 series FPGAs**
  • Demo board: Kintex-7 FPGA KC705 board**

** This course focuses on the 7 series FPGA architecture. The labs which require a demo board are targeted to use the Spartan-6 FPGA SP605, Virtex-6 FPGA ML605 board, or Avnet LX9 microboard. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Take advantage of the primary features of the 7 series FPGAs
  • Use the Xilinx Project Navigator to start a new project
  • Identify the available Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation)
  • Analyze designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power etc.)
  • Build custom IP with the IP Library utility
  • Make basic timing constraints (create_clock, set_input_delay, and set_output_delay)
  • Use the primary Tcl-based reports (check_timing,report_clock_interaction, report_clock_networks and report_timing_summary)
  • Describe and analyze common STA reports
  • Identify synchronous design techniques
  • Describe how an FPGA is configured

Course Outline


  • Design Methodology Summary
  • Basic FPGA Architecture
  • Introduction to the Vivado Design Suite
  • Vivado Design Flows
  • Lab 1: Vivado Tool Overview
  • Visualization of Analysis
  • Designing with IP
  • Basic Timing Constraints and Reports
  • Lab 2: Vivado Synthesis and Implementation
  • Clocking Wizard and Pin Assignment
  • Day 2
  • Designing with FPGA Resources
  • Clocking Resources
  • Lab 3a: Designing with FPGA Resources
  • Global Timing Constraints
  • Lab 3b: Creating an IP Integrator Subsystem Design
  • Basic Timing Constraints (XDC)
  • Timing Reports
  • Lab4: Basic XDC and Timing Reports
  • Synchronous Design Techniques
  • FPGA configuration
  • Course Summary
  • Appendix: SystemVerilog
  • Appendix: Design Methodology
  • Appendix: HDL Coding Techniques
  • Appendix: Using the Pin Planning Environment

Lab Descriptions

  • Lab 1: Vivado Tool Overview – Create a new project inVivado Design Suite. Add files, simulate, and elaborate the design. Review the available reports, analyze the design with the Schematic and Heirachy viewers, and run a design rule check (DRC). Finally, assign some of the I/O pins using the IO Planner.
  • Lab 2: Vivado Synthesis and Implementation-Synthesize and analyze the design with the Schematic viewer, review XDC timing constraints, and run basic static timing analysis. Implement the design and analyze with the Schematic viewer. Download the bitstream
  • Lab 3a: Designing with FPGA Resources-Use the Xilinx Clocking Wizard to configure a clocking subsystem to provide various clock outputs and clock buffers to connect clock signals to global clock networks
  • Lab 3b: Creating an IP Integrator Subsystem Design-Use the IP Integrator to create a complex system design by instantiating and interconnecting IPs from the Vivado IP Catalog on a design canvas.
  • Lab4: Basic XDC and Timing Reports- Use timing constraints to improve design performance. Perform static timing analysis before and after implementation to validate the performance results.

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Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.