Embedded Systems Design


EMBD-HW




Learn general embedded concepts, tools, and techniques using the Vivado® Design Suite and Vitis™ unified software platform.
The emphasis is on:
▪ Designing, expanding, and modifying embedded systems utilizing the features and capabilities of the Zynq® System on a Chip (SoC), Zynq UltraScale+™ MPSoC, or MicroBlaze™ soft processor
▪ Adding and simulating AXI-based peripherals using bus functional model (BFM) simulation.

What's New for 2021.2
▪ All labs have been updated to the latest software versions

 

Level – Embedded Hardware 3
Course Details
▪ 2 days ILT
▪ 17 lectures
▪ 8 labs
▪ 6 ILT demos
Price – $1600 or 16 credits
Course Part Number – EMBD-HW
Who Should Attend? – Engineers who are interested in developing
embedded systems with the Xilinx Zynq SoC, Zynq UltraScale+ MPSoC,
and/or MicroBlaze soft processor core
Prerequisites
▪ FPGA design experience
▪ Completion of the Designing FPGAs Using the Vivado Design
Suite 1 course or equivalent knowledge of Xilinx Vivado software implementation tools
▪ Basic understanding of C programming
▪ Basic understanding of microprocessors
▪ Some HDL modeling experience
Software Tools
▪ Vivado Design Suite 2021.2
▪ Vitis unified software platform 2021.2
Hardware
▪ Architectures: Zynq-7000 SoC (Cortex™-A9 processor), Zynq UltraScale+ MPSoC (Cortex-A53 and Cortex-R5 processors), and MicroBlaze processor*
▪ Demo board: Zynq UltraScale+ MPSoC ZCU104 or Versal® ACAP VCK190 board*

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the various tools that encompass a Xilinx embedded design 
  • Rapidly architect an embedded system containing a CortexA9/A53/R5 or MicroBlaze processor using the Vivado IP integrator and Customization Wizard 
  • Develop software applications utilizing the Eclipse-based Software Development Kit (SDK) 
  • Create and integrate an IP-based processing system component in the Vivado Design Suite 
  • Design and add a custom AXI interface-based peripheral to the embedded processing system 
  • Simulate a custom AXI interface-based peripheral using VIP

Course Outline 2021.2

Day 1

 Embedded UltraFast Design Methodology
Outlines the different elements that comprise the Embedded
Design Methodology. {Lecture, Demo}
▪ Overview of Embedded Hardware Development
Overview of the embedded hardware development flow. {Lecture,Demo}
Driving the IP Integrator Tool
Describes how to access and effectively use the IPI tool. {Lecture,Lab}
Overview of Embedded Software Development
Reviews the process of building a user application. {Lecture}
▪ Driving the SDK Tool
Introduces the basic behaviors required to drive the SDK tool to generate a debuggable C/C++ application. {Lecture, Lab}
AXI: Introduction
Introduces the AXI protocol. {Lecture}
AXI: Variations
Describes the differences and similarities among the three primary AXI variations. {Lecture}
▪ AXI: Transactions
Describes different types of AXI transactions. {Lecture, Lab,Demo}
Introduction to Interrupts
Introduces the concept of interrupts, basic terminology, and generic implementation. {Lecture}
Interrupts: Hardware Architecture and Support
Reviews the hardware that is typically available to help implement and manage interrupts. {Lecture}
 

 Day 2

AXI: Connecting AXI IP
Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies.
{Lecture, Demo}
Creating a New AXI IP with the Wizard
Explains how to use the Create and Import Wizard to create and package an AXI IP. {Lecture, Lab}
▪ AXI: BFM Simulation Using Verification IP
Describes how to perform BFM simulation using the Verification IP. {Lecture, Lab}
MicroBlaze Processor Architecture Overview
Overview of the MicroBlaze microprocessor architecture. {Lecture, Lab}
MicroBlaze Processor Block Memory Usage
Highlights how block RAM can be used with the MicroBlaze processor. {Lecture}
▪ Zynq-7000 SoC Architecture Overview
Overview of the Zynq-7000 SoC architecture. {Lecture, Demo,Lab}
▪ Zynq UltraScale+ MPSoC Architecture Overview
Overview of the Zynq UltraScale+ MPSoC architecture. {Lecture,Demo, Lab} 

 PDF version of this page.

Enroll Now.

Scheduled Embedded Courses

*FREE Workshop! Vitis and PetaLinux
August 23 : 10:00 am - 05:00 pm
After completing this workshop, you will have the necessary skills to:▪ Create an extensible...

Designing w/the DFX Using the Vivado Design Suite
August 29 - August 30: 09:00 am - 05:00 pm
Check with your local Authorized Training Provider for the specifics of the in-class lab board or...

Using Xilinx Alveo Cards to Accelerate Dynamic Workloads
August 31 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have the necessary skills to:▪ Describe the...

*Confirmed to run! Designing w/Versal ACAP: Architecture & Methodology
September 06 - September 09: 11:00 am - 05:00 pm
 After completing this comprehensive training, you will have thenecessary skills to:▪ Describe...

Zynq UltraScale+ MPSoC
September 06 - September 09: 11:00 am - 05:00 pm
Course DescriptionThis course provides an overview of the capabilities and support for the Zynq®...

Designing with Versal AI Engine 3:Kernel Programming & Optimization
September 15 - September 16: 09:00 am - 05:00 pm
This course covers the advanced features of the Versal™ ACAP AI Engine, including debugging an...

Designing with the Versal ACAP: PCI Express System
September 19 - September 20: 09:00 am - 05:00 pm
Course OutlineDay 1 ▪ Introduction to PCI ExpressIntroduces the course and discusses a few key...

*FREE Workshop! Using Vision-based App w/ the Kria KV260 Vision AI Starter Kit & SOM
September 21 - September 22: 10:30 am - 04:00 pm
After completing this comprehensive training, you will have the necessary skills to: ▪ Describe the...

*Confirmed to run! Designing FPGAs Using the Vivado Design Suite 2
September 26 - September 27: 09:00 am - 05:00 pm
This course shows you how to build an effective FPGA design using synchronous design techniques,...

Embedded Design with PetaLinux Tools
September 29 - September 30: 09:00 am - 05:00 pm
Level: Embedded Software 4 Course Duration: 2 days Price: $1600 or 16 Xilinx Training Credits...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.