Designing with Versal AI Engine 2

Designing with Versal AI Engine 2:Graph Programming w/AI Engine Kernels

ACAP-AIE2

Course Description

Level: ACAP 3
Course Duration: 2 days
Price: $1600 or 16 Xilinx Training Credits
Course Part Number: ACAP-AIE2
Who Should Attend?: – Software and hardware developers, system architects, and anyone wo needs to accelerate their software applications using Xilinx devices.


Registration: Register online in our secure store


Prerequisites

▪ Comfort with the C/C++ programming language
▪ Software development flow
▪ Vitis software for application acceleration development flow

Software Tools

  • Vitis Unifed software platform 2021.1

Hardware

  • Architecture Xilinx Versal ACAP's



After completing this comprehensive training, you will have the
necessary skills to:
▪ Describe the system-level flow, which includes PS + PL + AIE (SW-HW-SW) designs
▪ Describe the supported emulation for a system-level design
▪ Describe the data movement between the PS, PL, and AI Engines
▪ Describe the implementation of the AI Engine core and programmable logic
▪ Implement a system-level design for Versal ACAPs with the Vitis tool flow
▪ Utilize advanced MAC intrinsic syntax and application-specific intrinsics such as DDS and FFT
▪ Utilize the AI Engine DSP library for faster development
▪ Apply location constraints on kernels and buffers in the AI Engine array
▪ Apply runtime parameters to modify application behavior
▪ Debug a system-level design

Course Outline 2020.2


Day 1


▪ Application Partitioning on Versal ACAPs
Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal ACAP. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal ACAP. {Lecture}
ACAP Data Communication
Describes the implementation of AI Engine cores and the programmable logic (PL). Implement the functions in AI Engine that take advantage of low power.{Lecture}
System Design Flow
The Vitis compiler flow lets you integrate your compiled AI Engine design graph (libsdf.a) with additional kernels implemented in the PL region of the device, including HLS and RTL kernels, and link them for use on a target platform. You can call these compiled hardware functions from a host program running in the Arm® processor in the Versal device or on an external x86 processor.
{Lecture, Lab}
▪ Introduction to Advanced MAC Intrinsics
Describes how to implement filters using advanced intrinsics functions for various filters, such as non-symmetric FIR, symmetric FIR, half-band decimators. {Lecture, Labs}


Day 2


AI Engine Library Overview
Provides an overview of the DSP library available which enables faster development and comes with ready-to-use example designs which helps with using the library and tools. {Lecture,Lab}
▪ Advanced Graph Input Specification 1
Learn advanced features such as using initialization functions, writing directly using streams from the AI Engine, cascade stream, core location constraints, and buffer location constraints. {Lecture}
Advanced Graph Input Specification 2
Describes how to implement runtime parameterization, which can be used as adaptive feedback and switching functionality dynamically. {Lecture, Lab}
AI Engine Application Debug and Trace
Shows to how to debug the AI Engine application running on the Linux OS and how to debug via hardware emulation that allows simulation of the application. {Lecture, Demo}

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Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.