Designing with Versal AI Engine 2

Designing with Versal AI Engine 2:Graph Programming w/AI Engine Kernels


Course Description

Level: ACAP 3
Course Duration: 2 days
Price: $1600 or 16 Xilinx Training Credits
Course Part Number: ACAP-AIE2
Who Should Attend?: – Software and hardware developers, system architects, and anyone wo needs to accelerate their software applications using Xilinx devices.

Registration: Register online in our secure store


▪ Comfort with the C/C++ programming language
▪ Software development flow
▪ Vitis software for application acceleration development flow

Software Tools

  • Vitis Unifed software platform 2022.1


  • Architecture Xilinx Versal ACAP's

After completing this comprehensive training, you will have the
necessary skills to:
▪ Describe the system-level flow, which includes PS + PL + AIE (SW-HW-SW) designs
▪ Describe the supported emulation for a system-level design
▪ Describe the data movement between the PS, PL, and AI Engines
▪ Describe the implementation of the AI Engine core and programmable logic
▪ Implement a system-level design for Versal ACAPs with the Vitis tool flow
▪ Utilize advanced MAC intrinsic syntax and application-specific intrinsics such as DDS and FFT
▪ Utilize the AI Engine DSP library for faster development
▪ Apply location constraints on kernels and buffers in the AI Engine array
▪ Apply runtime parameters to modify application behavior
▪ Debug a system-level design

Course Outline 2022.1

Day 1

Design Analysis
▪ Application Partitioning on Versal ACAPs 1 (Review)
Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal  ACAP. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal ACAP. {Lecture}
Application Partitioning on Versal ACAPs 2
Explains how image and video processing can be targeted for the Versal ACAP by utilizing the different engines (Scalar Engine, Adaptable Engine, and Intelligent Engine). Also describes the AI engine development flow. {Lecture}
Versal AI Engine Data Movement
▪ ACAP Data Communications 1

Describes the implementation of AI Engine and programmable logic (PL) kernels and how to implement the functions in the AI Engine that take advantage of low power. {Lecture}
ACAP Data Communications 2
Describes the programming model for the implementation of stream interfaces for the AI Engine kernels and PL kernels. Lists the stream data types that aresupported by AI Engine and PL kernels. {Lecture, Lab}
Vitis Tool Flow
▪ System Design Flow

Demonstrates the Vitis compiler flow to integrate a compiled AI Engine design graph (libadf.a) with additional kernels implemented in the PL region of the device (including HLS and RTL kernels) and link them for use on a target platform. You can call then these compiled hardware functions from a host program
running in the Arm® processor in the Versal device or on an external x86 processor. {Lecture, Lab}
The Programming Model
▪ Introduction to AI Engine APIs for Arithmetic Operations

Describes the Versal AI Engine APIs for arithmetic, comparison, and reduction operations. For advanced users, describes how to implement filters using advanced intrinsics functions for various filters, such as non-symmetric FIRs, symmetric FIRs, or half-band decimators. {Lecture}

Day 2

▪ Versal AI Engine DSP Library Overview

Provides an overview of the available DSP library, which enables faster development and comes with ready-to-use example designs that help with using the library and tools. {Lecture, Labs}
The Programming Model
▪ Advanced Graph Input Specifications 1

Learn advanced features such as using initialization functions, writing directly using streams from the AI Engine, cascade stream, core location constraints, and buffer location constraints. {Lecture}
Advanced Graph Input Specifications 2
Describes how to implement runtime parameterization, which can be used as adaptive feedback and to switch functionality dynamically. {Lecture, Lab}
▪ Versal AI Engine Application Debug and Trace

Shows to how to debug the AI Engine application running on the Linux OS and how to debug via hardware


 PDF Version

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Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.