Designing with the Versal ACAP: Network on Chip

ACAP-NOC

Course Description

This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.
The emphasis of this course is on:
▪ Enumerating the major components comprising the NoC architecture in the Versal ACAP
▪ Implementing a basic design using the NoC
▪ Configuring the NoC for efficient data movement

Level: ACAP 2
Course Duration: 1 day
Price: $800 or 8 Xilinx Training Credits
Course Part Number: ACAP-NOC
Who Should Attend?: – Software and hardware developers, system
architects, and anyone who wants to learn about the architecture of the
Xilinx Versal ACAP device

Prerequisites
▪ Any Xilinx device architecture class
▪ Familiarity with the Vivado® Design Suite
Software Tools
▪ Vivado Design Suite 2020.2 Hardware
▪ Architecture: Xilinx Versal ACAPs


Registration: Register online in our secure store

 

 

After completing this comprehensive training, you will have the necessary skills to:
▪ Identify the major network on chip components in the Versal ACAP
▪ Include the necessary components to access the NoC from the PL
▪ Configure connection QoS for efficient data movement

Course Outline

Day 1

Architecture Overview for Existing Xilinx Users
Introduces to students that already have familiarity with Xilinx architectures to the new and updated features found in the Versal ACAP devices. {Lecture}
Versal ACAPs Compared to Zynq UltraScale+ Devices
The Versal ACAP has a number of similarities to the Zynq®
UltraScale+™ MPSoC devices. Understanding what is the same, what is different, and what is brand new helps put this powerful new part into context. {Lecture}
NoC Introduction and Concepts
Reviews the basic vocabulary and high-level operations of the NoC. {Lecture, Lab}
NoC Architecture
Provides the first deep dive into the sub-blocks of the NoC and how they are used. Describes how the NoC is accessed from the programmable logic. {Lecture}
Design Tool Flow Overview
Designers come to the Versal ACAP devices with different goals. This module explores how traditional FPGA designers, embedded developers, and accelerated system designers would use the various tools available in the Xilinx toolbox. {Lecture}
NoC DDR Memory Controller
The integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC's DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use. {Lecture}
NoC Performance Tuning
Synthesizes everything about the NoC and its DDRMCs, illustrating how to fine tune the NoC for the best performance. {Lecture, Lab}
System Design Migration
Describes how different users will leverage tools and processes to migrate their designs to the Versal ACAP devices. {Lecture}

  

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Scheduled Embedded Courses

Zynq UltraScale+ MPSoC
June 29 - July 01: 09:00 am - 05:00 pm
This course provides an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC...

*Confirmed to run! Designing with Versal AI Engine 1:Architecture & Design Flow
June 30 - July 01: 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to:▪ Describe the...

Designing with the Versal ACAP: PCI Express System
July 06 - July 07: 09:00 am - 05:00 pm
Course OutlineDay 1 ▪ Introduction to PCI ExpressIntroduces the course and discusses a few key...

Designing FPGAs Using the Vivado Design Suite 2
July 08 - July 09: 09:00 am - 05:00 pm
This course shows you how to build an effective FPGA design using synchronous design techniques,...

(Workshop) Embedded & Accelerating Applications w/Vitis Unified Software
July 12 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to: ▪ Implement...

Migrating to Vitis Embedded Software Development IDE
July 21 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to:▪ Develop and...

Designing with Versal AI Engine 3:Kernel Programming & Optimization
July 22 - July 23: 09:00 am - 05:00 pm
This course covers the advanced features of the Versal™ ACAP AI Engine, including debugging an...

Zynq UltraScale+ MPSoC
July 27 - July 29: 09:00 am - 05:00 pm
This course provides an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC...

*Confirmed to run! Designing w/the Versal ACAP: Power & Board Design
July 28 : 09:00 am - 05:00 pm
This course provides a system-level understanding of power and thermal issues related to designing...

Designing w/the DFX Using the Vivado Design Suite
July 29 - July 30: 09:00 am - 05:00 pm
Check with your local Authorized Training Provider for the specifics of the in-class lab board or...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.