Designing with the Versal ACAP: Network on Chip

ACAP-NOC

Course Description

This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.
The emphasis of this course is on:
▪ Enumerating the major components comprising the NoC architecture in the Versal ACAP
▪ Implementing a basic design using the NoC
▪ Configuring the NoC for efficient data movement

Level: ACAP 2
Course Duration: 1 day
Price: $800 or 8 Xilinx Training Credits
Course Part Number: ACAP-NOC
Who Should Attend?: – Software and hardware developers, system
architects, and anyone who wants to learn about the architecture of the
Xilinx Versal ACAP device

Prerequisites
▪ Any Xilinx device architecture class
▪ Familiarity with the Vivado® Design Suite
Software Tools
▪ Vivado Design Suite 2020.2 Hardware
▪ Architecture: Xilinx Versal ACAPs


Registration: Register online in our secure store

 

 

After completing this comprehensive training, you will have the necessary skills to:
▪ Identify the major network on chip components in the Versal ACAP
▪ Include the necessary components to access the NoC from the PL
▪ Configure connection QoS for efficient data movement

Course Outline

Day 1

Architecture Overview for Existing Xilinx Users
Introduces to students that already have familiarity with Xilinx architectures to the new and updated features found in the Versal ACAP devices. {Lecture}
Versal ACAPs Compared to Zynq UltraScale+ Devices
The Versal ACAP has a number of similarities to the Zynq®
UltraScale+™ MPSoC devices. Understanding what is the same, what is different, and what is brand new helps put this powerful new part into context. {Lecture}
NoC Introduction and Concepts
Reviews the basic vocabulary and high-level operations of the NoC. {Lecture, Lab}
NoC Architecture
Provides the first deep dive into the sub-blocks of the NoC and how they are used. Describes how the NoC is accessed from the programmable logic. {Lecture}
Design Tool Flow Overview
Designers come to the Versal ACAP devices with different goals. This module explores how traditional FPGA designers, embedded developers, and accelerated system designers would use the various tools available in the Xilinx toolbox. {Lecture}
NoC DDR Memory Controller
The integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC's DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use. {Lecture}
NoC Performance Tuning
Synthesizes everything about the NoC and its DDRMCs, illustrating how to fine tune the NoC for the best performance. {Lecture, Lab}
System Design Migration
Describes how different users will leverage tools and processes to migrate their designs to the Versal ACAP devices. {Lecture}

  

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Scheduled Embedded Courses

Zynq SoC System Architecture
April 28 - April 29: 09:00 am - 05:00 pm
* This course focuses on the Zynq-7000 SoC. Check with your local Authorized Training Provider for...

Designing with the Versal ACAP: Power & Board Design
May 07 : 09:00 am - 05:00 pm
This course provides a system-level understanding of power and thermal issues related to designing...

Designing with Versal AI Engine 1:Architecture & Design Flow
May 11 - May 12: 09:00 am - 05:00 pm
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(Workshop) Embedded & Accelerating Applications w/Vitis Unified Software
May 17 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to: ▪ Implement...

Zynq UltraScale+ MPSoC
May 18 - May 20: 10:00 am - 06:00 pm
This course provides an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC...

Accelerating Applications with the Vitis Unified Software Environment
May 27 - May 28: 09:00 am - 05:00 pm
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™...

Designing with the Versal ACAP: NoC
June 02 : 09:00 am - 05:00 pm
This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx...

Embedded Design with PetaLinux Tools
June 03 - June 04: 09:00 am - 05:00 pm
Level: Embedded Software 4 Course Duration: 2 days Price: $1600 or 16 Xilinx Training Credits...

Designing with Versal AI Engine 2:Graph Programming w/AI Engine Kernels
June 10 - June 11: 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to:▪ Describe the...

Designing with Versal AI Engine 3:Kernel Programming & Optimization
June 30 - July 01: 09:00 am - 05:00 pm
This course covers the advanced features of the Versal™ ACAP AI Engine, including debugging an...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.