Designing with the IP Integrator Tool

Designing with the IP Integrator Tool

FPGA IPI

Course Description

Explore the IP integrator tool and its features to gain the expertise needed to develop, implement, and debug different IPI block designs using the Vivado® Design Suite.
This course focuses on:
▪ Creating an IPI block design using the Vivado Design Suite
▪ Creating your own custom IP via the IP packaging flow
▪ Using the IP integrator to add and configure the Versal™ ACAP CIPS block and then to export the generated programmable device image (PDI)
▪ Configuring the AXI network on chip (NoC) to access DDR memory controllers in Versal ACAP devices

Course Details

  • 1 Day $800 or 8 Training Credits
  • 9 lectures
  • 5 labs
  • 2 demos

Course Part Number – FPGA-IPI
Who Should Attend? – Software and hardware developers, system architects, and anyone who wants to learn about the Vivado Design Suite IP integrator tool
Prerequisites
▪ Basic FPGA and Vivado Design Suite knowledge
Software Tools
▪ Vivado Design Suite 2021.1
▪ Vitis unified software platform 2021.1
Hardware
▪ Architecture: UltraScale™ family and Versal ACAPs
▪ Demo board: Zynq® UltraScale+™ ZCU104 board

After completing this comprehensive training, you will have the
necessary skills to:

▪ Describe the Vivado tool flow for RTL-based and IP-based design flows
▪ Create a Vivado IP integrator block design using the Vivado
Design Suite
▪ Describe the block design container feature in the IP integrator
▪ Package custom IP and add it to the IP catalog repository or manage it in a remote location
▪ Use the IP integrator to add and configure the Versal ACAP CIPS block and export the generated hardware
▪ Configure the AXI NoC to access DDR memory controllers in Versal ACAP devices
▪ Use a revision control system in the Vivado Design Suite flows
▪ Use the IP integrator to add debug cores to an existing block design to debug the design

Course Outline

Vivado IP Catalog
▪ Vivado IP Flow
Customize IP, instantiate IP, and verify the hierarchy of your design IP. {Lecture, Demo}
IP Integrator
▪ Designing with the IP Integrator
Use the Vivado IP integrator to create the uart_led subsystem. {Lecture, Demo, Lab}
▪ Block Design Containers in the Vivado IP Integrator
Describes the block design container (BDC) feature and shows how to create a BDC in the IP integrator. {Lecture}
▪ Creating and Packaging Custom IP
Create your own IP and package and include it in the Vivado IP catalog. {Lecture, Lab}
▪ Versal ACAP: Hardware Platform Development Using the
Vivado IP Integrator
Describes the different Versal ACAP design flows and covers the platform creation process using the Vivado IP integrator. {Lecture, Lab}
▪ Versal ACAP: NoC Introduction and Concepts
Reviews the basic vocabulary and high-level operations of the NoC. {Lecture, Lab}
Debugging
▪ Debug Flow in an IP Integrator Block Design
Insert the debug cores into IP integrator block designs. {Lecture, Lab}
Version Control Systems
▪ Revision Control Systems in the Vivado Design Suite
Use version control systems with Vivado design flows. {Lecture}
Vivado IP Catalog
▪ Managing IP in Remote Locations
Store IP and related files remote to the current working project directory. {Lecture}

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Scheduled Embedded Courses

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February 02 : 09:00 am - 05:00 pm
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Designing FPGAs Using the Vivado Design Suite 2
February 10 - February 11: 09:00 am - 05:00 pm
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Designing with the IP Integrator Tool
February 18 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have the necessary skills to:▪ Describe the...

Accelerating Applications with the Vitis Unified Software Environment
February 23 - February 25: 09:00 am - 05:00 pm
After completing this comprehensive training, you will have the necessary skills to:▪ Describe how...

Designing w/the Xilinx Serial Transceivers
February 28 - March 01: 09:00 am - 05:00 pm
Learn how to employ serial transceivers in UltraScale™ and UltraScale+™ FPGA designs or Zynq®...

Designing w/the DFX Using the Vivado Design Suite
March 03 - March 04: 09:00 am - 05:00 pm
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Using Xilinx Alveo Cards to Accelerate Dynamic Workloads
March 07 : 09:00 am - 05:00 pm
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Zynq UltraScale+ MPSoC
March 07 - March 10: 11:00 am - 05:00 pm
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Kria KV260 Vision AI Starter Kit & Som
March 08 : 09:00 am - 05:00 pm
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Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.