Designing with SystemVerilog

LANG-SVDES

Course Description

This course provides a thorough introduction to SystemVerilog
constructs for design.
This focus is on:
▪ Writing RTL code using the new constructs available in
SystemVerilog
▪ Reviewing new data types, structs, unions, arrays, procedural
blocks, re-usable tasks, functions, and packages
▪ Targeting and optimizing Xilinx devices using SystemVerilog
What's New for 2021.1
▪ All labs have been updated to the latest software versions

Level: FPGA 1
Course Duration: 2 days
Price: $1600 or 16 Xilinx Training Credits
Course Part Number: LANG-SVDES-ILT
Who Should Attend?: FPGA designers and logic designers
Registration: Register online in our secure store

Prerequisites

Verilog design experience or completion of Designing with Verilog

Software Tools

Vivado® Design or System Edition 2021.1
Questa Sim Prime Simulator 2019.4

Hardware

Architecture: N/A*
Demo board: Kintex® UltraScale™ FPGA KCU105

* This course does not focus on any particular architecture. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

Describe the features and benefits of using SystemVerilog for RTL design
Identify the new data types supported in SystemVerilog
Use an enumerated data type for coding a finite state machine (FSM)
Explain how to use structures, unions, and arrays
Describe the new procedural blocks and analyze the affected synthesis results
Define the enhancements and ability to reuse tasks, functions, and packages
Identify how to simplify module definitions and instantiations using interfaces
Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
Target and optimize Xilinx FPGAs by using SystemVerilog
Synthesize and analyze SystemVerilog designs with the Vivado Design Suite
Download a complete SystemVerilog design to an evaluation board

Course Outline

Day 1

Introduction to SystemVerilog

Provides an introduction to the SystemVerilog language. {Lecture}

Data Types

Describes the data types supported by SystemVerilog. {Lecture, Lab, Demo}

User-Defined and Enumerated Data Types Describes user-defined and enumerated data types supported by

SystemVerilog. {Lecture}

Type Casting

Describes type casting in SystemVerilog. {Lecture}

Arrays and Strings

Explains the use of arrays in SystemVerilog. {Lecture}

SystemVerilog Building Blocks

Describes the design and verification building blocks in SystemVerilog. {Lecture}

Structures

Explains the use of structures in SystemVerilog. {Lecture, Lab}

Unions

Explains the use of unions in SystemVerilog. {Lecture, Lab}

Additional Operators in SystemVerilog

Describes the operators supported by SystemVerilog beyond those found in Verilog. {Lecture}

Day 2

Procedural Statements

Describes the different procedural blocks provided by SystemVerilog. {Lecture, Lab}

Control Flow Statements

Describes the different control statements provided by SystemVerilog. {Lecture}

Functions

Explains the SystemVerilog enhancements to functions. {Lecture}

Tasks

Describes the task SystemVerilog construct. {Lecture}

Packages

Describes the package SystemVerilog construct. {Lecture, Lab}

Interfaces

Describes the concept of interfaces in SystemVerilog. {Lecture}

Targeting Xilinx FPGAs

Focuses on Xilinx-specific implementation and chip-level optimization. {Lecture, Lab}

PDF version of this page.

Enroll Now.

Scheduled Language Courses

No courses of this type are currently scheduled

No events found.

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates. If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs. No obligation necessary.