Xilinx Training Courses

Faster Technology is the Xilinx Authorized Training Provider (ATP) for the South Central (Texas, Louisiana, Oklahoma, and Arkansas) and Rocky Mountain (Colorado, Utah, Montana, and Wyoming) regions of the United States.

As a Xilinx ATP, Faster Technology delivers the following full line of Xilinx training courses in the areas of FPGA Design, Embedded Systems Development, Connectivity, DSP Design, MPSoC, SDSoC and Languages.

 *Please note that if a class doesn't have enough enrollment for onsite, it may be converted to online.

(Click on the following links for course specific information

*NEW* Proficiency Stacks : Applied Learning Labs

• Designing FPGAs w/Vivado Suite 1 & 2
• Designing FPGAs w/Vivado Suite 3 & 4
• HLS C/C++ High Level Synthesis Vitis & Vivado
• Versal:ACAP AI Engine 1, 2 & 3
• Zynq US+ MPSoC Hardware & Software
• Versal:ACAP Architecture & Methodology
• 
  Systems and Solutions Planning (New)
  
  Kria KV260 Vision AI Starter Kit & SoM
• Using Xilinx Alevo Cards to Accelerate Dynamic Workloads
• Designing w/DFX Using the Vivado Design Suite
• Designing with the Versal ACAP: Architecture and Methodology
• Developing Multimedia Solutions w/the Video Codec
• Designing w/the Versal ACAP: Power & Board Design
• Developing Xilinx AI Solutions for Cloud-based Applications
• Developing Xilinx AI Solutions for Edge-based Applications
• Designing w/the Versal ACAP:PCI Express System
• Designing with Versal ACAP:NoC
• Designing with Versal AI Engine 1:Archtecture and Design Flow
• Designing with Versal AI Engine 2:Graph Programming w/AI Engine Kernels
• Designing with Versal AI Engine 3:Kernel Programming & Optimization

 Machine Learning & Data Science (New)

• Developing AI Inference Solutions w/the Vitis AI Platform

 AI Engine Development (New)

• Designing with Versal AI Engine 1:Archtecture and Design Flow
• Designing with Versal AI Engine 2:Graph Programming w/AI Engine Kernels
• Designing with Versal AI Engine 3:Kernel Programming & Optimization

  Host SW Development (New)

• Accelerating Applications with Vitis Unified Software Environment
• Developing AI Inference Solutions w/the Vitis AI Platform
• Vitis Acceleration and Alveo (not released yet)

 Hardware, IP, and Development Platform

• Designing with the IP Integrator Tool
• High-Level Synthesis w/the Vitis HLS Tool (New)
• Designing with Verilog
• Designing with SystemVerilog

FPGA Design Courses

ISE Courses

• Essentials of FPGA Design
• Designing for Performance
• Advanced FPGA Implementation

Vivado Design Suite

• Essential Tcl Scripting for Vivado Design Suite
• Designing FPGAs Using the Vivado Design Suite 1
• Designing FPGAs Using the Vivado Design Suite 2
• Designing FPGAs Using the Vivado Design Suite 3
• Designing FPGAs Using the Vivado Design Suite 4
• Partial Reconfiguration Tools and Techniques

Vivado Adoptor Courses

• Ultrafast Design Methodology
• Vivado Design Suite for ISE Project Navigator Users
• Vivado Design Suite - Advanced XDC and Timing Analysis for ISE Users 

Architecture Courses

• Designing with the Spartan-6 and Virtex-6 Families
• Designing with the Spartan-6 Family
• Designing with the Virtex-6 Family
• Designing with the 7 Series Families
• UltraScale and UltraScale+ Architectures Workshop
• Designing with the UltraScale and UltraScale+ Architectures

Embedded Systems Development 

• Embedded Systems Design 
• Advanced Features and Techniques of Embedded Systems Design
• Embedded Systems Software Design
• Advanced Features and Techniques of Embedded Systems Software Development
• Introduction to the Zynq SoC Architecture
• Zynq SoC System Architecture
• Embedded Design with PetaLinux 
• SDSoC Development Environment & Methodology
• Zynq UltraScale+MPSoC-Software Developer
• Zynq UltraScale+MPSoC-System Architect
• Zynq UltraScale+MPSoC for the Hardware Designer
• Zynq UltraScale+MPSoC
• Accelerating C, C++, OpenCL, and RTL Applications with the SDAccel Environment
• Migrating to the Vitis Development Software IDE

Connectivity Courses 

• PCIe Protocol Overview
• Designing an Integrated PCI Express® System
• Designing with Multi-Gigabit Serial I/O
• Designing with Xilinx Serial Transceivers
• Signal Integrity and Board Design for Xilinx FPGAs
• How to Design a High-Speed Memory Interface 
• Designing with Ethernet MAC Controllers 
• Designing with the Zynq UltraScale RFSoC

DSP Design Courses 

• DSP Design Using System Generator 
• Essential DSP Implementation Techniques for Xilinx FPGAs 

Language Courses

• Designing with Verilog 
• Designing with VHDL 
• Advanced VHDL 
• Designing with SystemVerilog
• Verification with SystemVerilog

Private Classes 

• Custom On-Site Training

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes that are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.

Student Cancellation Policy

Student cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.

Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.

Student cancellations must be sent to registrar(at)fastertechnology.com

Faster Technology Course Cancellation Policy

Due to low class size and other certain considerations, Faster Technology may cancel a class up to 7 days before the scheduled start date of the class.  In such cases, all students will be entitled to a 100% refund.  Faster Technology will notify registered students of "at risk" classes prior to cancellation.

 *Please note that if a class doesn't have enough enrollment for onsite, it may be converted to online.

Under no circumstances is Faster Technology responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.