Designing with SystemVerilog
This comprehensive course is a thorough introduction to SystemVerilog constructs for design. This class addresses writing RTL code using the new constructs avail in SystemVerilog. New data types, structs,unions,arrays,procedural blocks, re-usable tasks, functions and packages, are all covered. The information gained can be applied to any digital design, This course combines insightful lectures with practical lab exercises to reinforce key concepts. This two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop RTL designs.
Course details with outline, daily schedule and prerequisites.
Currently Scheduled Classes
Designing with SystemVerilog July 18-19th-2022 Online
Title: Designing with SystemVerilog
Date/Duration: July 18-19th, 2022 Two Days
Times: 9 AM - 5 PM
Location: Online