This free workshop (delivered in 2 half day sessions) explores the power and capabilities of High-Level Synthesis (AMD Vitis™ HLS) to dramatically accelerate embedded software to hardware speeds.
It will provide an overview of the HLS design process, explain the component development flow, demonstrate how to explore design alternatives using directives and provide an introduction to interfacing the accelerated hardware block.
Further details will be provided to optimize performance by optimizing dataflows and pipelining.
The workshop is designed to maximize individual engagement and learning. Each attendee is encouraged to informally ask pertinent questions throughout, to actively participate in the learning process.
