UltraFast Design Metholology

UltraFast Design Methodology

FPGA-VDM

Course Description

Learn how to improve design speed and reliability by using the UltraFast Design Methodology and the Vivado® Design Suite.
The focus is on:
▪ Optimizing system reset design and synchronization circuits
▪ Employing best practice HDL coding techniques
▪ Applying appropriate timing closure techniques
▪ Reviewing an UltraFast Design Methodology case study
What's New for 2019.2
▪ Vivado Design Suite I/O Pin Planning: Information on simultaneous switching noise (SSN) predictor tool
▪ UltraFast Design Methodology – Design Creation: Auto-pipelining considerations
▪ Designing with IP Integrator: Additional description of IPI features
▪ Timing Closure Using Physical Optimization Techniques: Clarification on PhysOpt option enablement

 

Level: FPGA 3 
Course Duration: 2 day
Price: $1600 or 16 Xilinx Training Credits
Course Part Number: FPGA-VDM
Who Should Attend?:Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.
Registration: Register online in our secure store

Prerequisites

Basic HDL knowledge (VHDL or Verilog)
▪ Digital design knowledge and experience
▪ Vivado Design Suite experience or completion of either:
○ Designing FPGAs Using the Vivado Design Suite 1 course and
○ Designing FPGAs Using the Vivado Design Suite 2 course and
○ Designing FPGAs Using the Vivado Design Suite 3 course or
○ Vivado Design Suite Advanced XDC and Static Timing Analysis
for ISE Software Users course

Software Tools

  • Vivado Design or System Edition 2019.2

Hardware

  • Architecture: UltraScale and 7 series FPGAs*
  • Demo board: None

*This course focuses on the 7 series FPGA architectures. Contact us for the specifics of the in-class lab board or other customizations.

 * This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for specifics or other customizations.

After completing this comprehensive training, you will have the necessary skills to:
▪ Describe the UltraFast™ design methodology checklist
▪ Identify key areas to optimize your design to meet your design goals and performance objectives
▪ Define a properly constrained design
▪ Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
▪ Build resets into your system for optimum reliability and design speed
▪ Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
▪ Identify timing closure techniques using the Vivado Design Suite
▪ Describe how the UltraFast design methodology techniques work effectively through case studies and lab experience

Course Outline

Day 1

UltraFast Design Methodology: Introduction
Introduces the UltraFast Design Methodology and the Ultrafast Design Methodology checklist. {Lecture, Demo}
▪ UltraFast Design Methodology: Board and Device Planning
Introduces the methodology guidelines on board and device planning. {Lecture}
▪ Vivado Design Suite I/O Pin Planning
Use the I/O Pin Planning layout to perform pin assignments in a design. {Lecture, Lab}
▪ Xilinx Power Estimator Spreadsheet
Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE. {Lecture, Lab}
▪ Introduction to FPGA Configuration
Describes how FPGAs can be configured. {Lecture}
▪ UltraFast Design Methodology: Design Creation
Introduces the UltraFast methodology guidelines on design creation. {Lecture}
▪ HDL Coding Techniques
Covers basic digital coding guidelines used in an FPGA design. {Lecture}
Resets
Investigates the impact of using asynchronous resets in a design. {Lecture, Lab}
▪ Register Duplication
Use register duplication to reduce high fanout nets in a design. {Lecture}
▪ Pipelining
Use pipelining to improve design performance. {Lecture, Lab}
▪ Synchronous Design Techniques
Introduces synchronous design techniques used in an FPGA design. {Lecture}
▪ Creating and Packaging Custom IP
Create your own IP and package and include it in the Vivado IP catalog. {Lecture}

Day 2

▪ Designing with the IP Integrator
Use the Vivado IP integrator to create the uart_led subsystem. {Lecture, Lab}
▪ Revision Control Systems in the Vivado Design Suite
Use version control systems with Vivado design flows. {Lecture}
▪ UltraFast Design Methodology: Implementation
Introduces the methodology guidelines on implementation. {Lecture}
▪ Vivado Synthesis and Implementation
Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board. {Lecture} Incremental Compile Flow Utilize the incremental compile flow when making last-minute RTL changes. {Lecture}
▪ UltraFast Design Methodology: Design Closure
Introduces the UltraFast methodology guidelines on design closure. {Lecture}
▪ Introduction to Vivado Reports
Generate and use Vivado reports to analyze failed paths. {Lecture, Demo}
▪ Baselining
Use Xilinx-recommended baselining procedures to progressively meet timing closure. {Lecture, Lab}
▪ Introduction to Timing Exceptions
Introduces timing exception constraints and applying them to fine tune design timing. {Lecture, Demo, Lab}
▪ Synchronization Circuits
Use synchronization circuits for clock domain crossings. {Lecture}
▪ Introduction to Floorplanning
Introduction to floorplanning and how to use Pblocks while floorplanning. {Lecture}
▪ Congestion
Identifies congestion and addresses congestion issues. {Lecture}
▪ Timing Closure Using Physical Optimization Techniques
Use physical optimization techniques for timing closure. {Lecture}
▪ Power Management Techniques
Identify techniques used for low power design. {Lecture}
▪ Vivado Design Suite Debug Methodology
Understand and follow the debug core recommendations. Employ the debug methodology for debugging a design using the Vivado logic analyzer. {Lecture}

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Scheduled FPGA Courses

C-Based Design: High-Level synthesis with the Vivado HLx Tool
April 14 - April 15: 09:00 am - 05:00 pm
v2018.2 This course provides a through introduction to the Vivado High-Level Synthesis (HLS) tool....

Private Onsite
April 20 - April 22: 09:00 am - 05:00 pm
* v2016.1 This course provides a through introduction to the Vivado High-Level Synthesis (HLS)...

C-Based Design: High-Level synthesis with the Vivado HLx Tool
May 12 - May 13: 09:00 am - 05:00 pm
v2018.2 This course provides a through introduction to the Vivado High-Level Synthesis (HLS) tool....

Designing with the UltraScale Architecture 2018.3
June 11 - June 12: 09:00 am - 05:00 pm
This course introduces new and experienced designers to the most sophisticated aspects of the...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.