Designing with the Spartan-6 Family

FPGA 3 | S6-21000-13-ILT (v1.0)

Course Description

Are you interested in learning how to effectively utilize Spartan®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in this popular device family.  

Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (PCI Express® technology, memory controller block, and GTP transceivers) are also introduced.

This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.

Level: FPGA 3
Course Duration: 2 days
Price: $1600 or 16 Xilinx Training Credits
Course Part Number: S6-21000-13-ILT
Who Should Attend?: For those who have taken the Essentials of FPGA Design course.
Registration: Register online in our secure store


Software Tools

  • Xilinx ISE® Design Suite: Logic or System Edition 13.1


  • Architecture: Spartan-6 FPGA*
  • Demo board: None*

* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Describe all the functionality of the 6-input LUT and the CLB construction of the Spartan-6 FPGA
  • Specify the CLB resources and the available slice configurations
  • Define the block RAM and DSP resources available for the Spartan-6 FPGA
  • Properly design for the I/O block and SERDES resources
  • Identify the DCM, PLL, and clock routing resources included with this family
  • Identify the features and supported memory controllers of the hard memory controller block
  • Properly code your HDL to get the most out of the Spartan-6 FPGA
  • Describe the additional dedicated hardware for all the Spartan-6 family members

Course Outline

Day 1

  • Spartan-6 FPGA Overview
  • CLB Architecture
  • HDL Coding Techniques
  • Lab 1: CLB Resources
  • Memory Resources
  • DSP Resources
  • Lab 2: DSP Resources
  • Basic I/O Resources
  • Spartan-6 FPGA I/O Resources

Day 2

  • Lab 3: I/O Resources
  • Basic Clocking Resources
  • Spartan-6 FPGA Clocking Resources
  • Lab 4: Clocking Resources
  • Memory Controllers
  • Dedicated Hardware

Lab Descriptions

  • Lab 1: CLB Resources – Using XST, synthesize a 32-bit incrementer with terminal count logic and pipelining registers. Verify that the appropriate resources were used with the RTL and technology viewers included with XST. Use the FPGA Editor to inspect the implemented results.
  • Lab 2: DSP Resources – Using XST, synthesize and implement a 17x17 MACC. Device usage will be verified via the FPGA Editor. Using the CORE Generator™ tool, construct, instantiate, and implement a wide pipelined multiplier. Verify the results with the FPGA Editor.
  • Lab 3: I/O Resources– Using the ISE tools, complete the construction of the transmit SERDES datapath. Explore, through simulation, the behavior of the various blocks. Also use the FPGA Editor to explore the physical resources of the Spartan-6 FPGA used for construction of a high-speed interface.
  • Lab 4: Clocking Resources – Using the Clocking Wizard, build and optimize the appropriate PLL, DCM, and clock routing resources. Also instantiate these resources into the design. After the design is implemented, verify hardware usage with the FPGA Editor and explore other aspects of the silicon layout.

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Scheduled FPGA Courses

C-Based Design: High-Level synthesis with the Vivado HLx Tool
April 14 - April 15: 09:00 am - 05:00 pm
v2018.2 This course provides a through introduction to the Vivado High-Level Synthesis (HLS) tool....

Private Onsite
April 20 - April 22: 09:00 am - 05:00 pm
* v2016.1 This course provides a through introduction to the Vivado High-Level Synthesis (HLS)...

C-Based Design: High-Level synthesis with the Vivado HLx Tool
May 12 - May 13: 09:00 am - 05:00 pm
v2018.2 This course provides a through introduction to the Vivado High-Level Synthesis (HLS) tool....

Designing with the UltraScale Architecture 2018.3
June 11 - June 12: 09:00 am - 05:00 pm
This course introduces new and experienced designers to the most sophisticated aspects of the...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.