Migrating from ISE & Spartan 6 to Vivado & 7 Series

FTLFPGA-S6-CUST

Course Description

Level: FPGA 2
Course Duration: 1 day
Price: $800 or 8 Xilinx Training Credits
Course Part Number: FTLFPGA-S6-CUST
Who Should Attend? – For those who want to migrate legacy Spartan 6 designs to newer Xilinx technologies
Prerequisites
▪ Basic Spartan-6 architecture knowledge
▪ Basic ISE or PlanAhead design entry knowledge
Software Tools
▪ Vivado® Design Suite 2021.1
Hardware
▪ Architecture: Spartan-6, 7 Series, and cost optimized UltraScale+
▪ Demo board: None

 

 

 After completing this comprehensive training, you will have the
necessary skills to:
▪ Analyze Spartan-6 designs and identify the critical parts of the design and how to update them for newer Xilinx devices
▪ Migrate to new clocking, IO, and other key resources
▪ Rewrite UCF constraints using the new XDC format
▪ Use the Xilinx Baselining method to close timing
▪ Use the new Vivado IP Catalog to instantiate IP

Course Outline
▪ ISE versus Vivado Design Flow
▪ Vivado Design Suite Project Mode
▪ Clocking Resource Migration
▪ I/O Resource Migration
▪ UCF to XDC Constraints
▪ LAB/Demo: Vivado XDC Constraints Editor
▪ CoreGen to Vivado IP Catalog
▪ Lab/Demo: IP Flow
▪ Vivado Timing Reports
▪ Baselining Approach to Timing Closure

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Scheduled FPGA Courses

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.