Designing with the Zynq UltraScale+ RFSoC

Designing with the Zynq UltraScale+ RFSoC 

Course Part Number-CONN-RFSOC

Course Description

This course is structured to provide designers with an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family. Special emphasis is placed on the Data Converter and Soft-Decision FEC blocks.  Power estimation is covered to help designers identify the power demands of the device in various operating modes. Since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device, proper layout and PCB considerations are also covered

Level: Connectivity 3 

Course Duration: 2 days 

Price: $1600 or 16 Xilinx Training Credits
Course Part Number: CONN-RFSOC 
Who Should Attend?: Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ RFSoC data converter and SD-FEC hard blocks. 


Registration: Register online in our secure store

Prerequisites

    • Suggested: Understanding of the Zynq UltraScale+ MPSoC architecture 
    • Basic familiarity with data converter terms and principles 
    • Basic familiarity with forward error correction terms and principles

Software Tools

  •  Vivado Design Suite 2018.1

Hardware

  • Host computer for running the above software*

 Contact us for the specifics of the in-class lab board or other customizations.

* This course focuses on the Zynq UltraScale+ RFSoC architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab environment or other customizations.  After completing this comprehensive training, you will have the necessary skills to: 

▪ Describe in general the new Zynq UltraScale+ RFSoC family 

▪ Identify typical applications for the data converters 

▪ Describe the architecture and functionality of the ADC 

▪ Utilize the ADC via configuration, simulation, and implementation 

▪ Describe the architecture and functionality of the DAC 

▪ Utilize the DAC via configuration, simulation, and implementation 

▪ Identify the requirements and options for data converter PCB designs 

▪ Describe the architecture and functionality of the SD-FEC hard IP 

▪ Utilize the SD-F

Course Outline

▪ Zynq UltraScale+ RFSoC Overview {Lectures}  

▪ RFSoC ADC {Lectures, Demo, Lab} 

▪ RFSoC DAC {Lectures, Demo, Lab} 

▪ RFSoC Data Converter Design {Lectures, Labs} 

▪ PCB Design for RFSoC Devices {Lectures} 

▪ RFSoC SD-FEC {Lectures, Demo, Lab} 

 

Topic Descriptions

  Zynq UltraScale+ RFSoC Overview – Overview of the Zynq UltraScale+ RFSoC architecture, including brief introductions to RF, data converter solutions, SD-FEC solutions, driver support, and tool support. 

▪ RF-ADC – Covers the basics of ADCs. Reviews ADC architecture, functionality, interfaces, configuration, and driver support. 

▪ RF-DAC – Covers the basics of DACs. Reviews DAC architecture, functionality, interfaces, configuration, and driver support. 

▪ Data Converter Design – Describes common features, the design flow, and utilizing the example design by simulation and implementation. 

▪ PCB Design for RFSoC Devices – Describes power requirements, performing power estimation, and utilizing the power design. Analog signal requirements, PCB materials and layer stackup options, and analog trace design are also covered. 

▪ Soft-Decision FEC – Covers the basics of forward error correction. Reviews SD-FEC architecture, functionality, interfaces, configuration, and driver support. 


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Scheduled Embedded Courses

Zynq UltraScale+MPSoC-Software Developer
March 03 - March 04: 09:00 am - 05:00 pm
v2016.3 This two-day course is structured to provide software designers with a catalog of OS...

Zynq UltraScale+MPSoC-System Architect
March 05 - March 06: 09:00 am - 05:00 pm
This two-day online course is structured to provide system architects with an overview of the...

(Workshop) Embedded & Accelerating Applications w/Vitis Unified Software
March 16 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to: ▪ Implement...

Designing FPGAs Using the Vivado Design Suite 3
March 17 - March 18: 09:00 am - 05:00 pm
This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

(Workshop) Embedded & Accelerating Applications w/Vitis Unified Software
March 24 : 09:00 am - 05:00 pm
After completing this comprehensive training, you will have thenecessary skills to: ▪ Implement...

Zynq UltraScale+MPSoC-Software Developer-Online
April 09 - April 10: 09:00 am - 05:00 pm
This two-day course is structured to provide software designers with a catalog of OS implementation...

Designing FPGAs Using the Vivado Design Suite 3
April 16 - April 17: 09:00 am - 05:00 pm
This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

Accelerating Applications with the Vitis Unified Software Environment
April 23 - April 24: 09:00 am - 05:00 pm
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™...

Accelerating Applications with the Vitis Unified Software Environment
April 28 - April 29: 09:00 am - 05:00 pm
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™...

Zynq UltraScale+MPSoC-Software Developer
April 30 - May 01: 09:00 am - 05:00 pm
This two-day course is structured to provide software designers with a catalog of OS implementation...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.