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FM-S18 Reference Design for VC707

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: 04. 08. 2015 [11:56]
Topic creator
registered since: 04.08.2015
Posts: 1
Hello everyone,
I just downloaded your reference design for the VC707 to investigate in my own design. You are using pin C9 & C10 for the Q15_CLK1_MGTREFCLK signals, but in the Xilinx UG885 p.88 they use E9 & E10. Also in the schematics.
Actually I'm using Vivado so i'm not able to debug your design properly, because my ISE is complaining about my licence and stuff, I don't know. If you have a reference design for vivado I'd be glad about a download link.
A big thanks from Germany.
: 31. 05. 2017 [12:48]
registered since: 31.05.2017
Posts: 1