Designing with SystemVerilog July 18-19th-2022 Online
Details
This course provides a thorough introduction to SystemVerilog constructs for design. This focus is on: ▪ Writing RTL code using the new constructs available in SystemVerilog ▪ Reviewing new data types, structs, unions, arrays, procedural blocks, re-usable tasks, functions, and packages ▪ Targeting and optimizing Xilinx devices using SystemVerilog What's New for 2021.1 ▪ All labs have been updated to the latest software versions
Additional Information
Custom Stock Status | No |
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