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Designing FPGAs Using the Vivado Design Suite 4 December 13-14, 2021 Online

Designing FPGAs Using the Vivado Design Suite 4 December 13-14, 2021 Online

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Availability: In stock

$1,600.00

Quick Overview

Title: Designing FPGAs with the Vivado Design Suite 4
Date/Duration: December 13-14-2021, Two days
Times: 9 AM - 5 PM
Location:  Online

Designing FPGAs Using the Vivado Design Suite 4 December 13-14, 2021 Online

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$1,600.00

Details

Learn how to use the advanced aspects of the Vivado® Design Suite and Xilinx hardware. The focus is on: ▪ Applying timing constraints for source-synchronous and system-synchronous interfaces ▪ Utilizing floorplanning techniques ▪ Employing advanced implementation options ▪ Utilizing Xilinx security features ▪ Identifying advanced FPGA configurations ▪ Debugging a design at the device startup phase ▪ Using Tcl scripting in non-project batch flows This is the final course in the Designing FPGAs Using the Vivado Design Suite series. What's New for 2021.1 ▪ UltraFast Design Methodology - Design Closure: Added information about the Intelligent Design Run (IDR) flow for design closure ▪ Versal ACAP - Power Management: Added new module to discuss power management in Versal™ ACAP devices ▪ Versal ACAP - Debugging: Added new module and lab to describe the high-speed debug port (HSDP) and how to configure a CIPS block to enable the HSDP ▪ Introduction to the Vivado Store: Updated information on the Vivado Store (formerly the XHub Stores) ▪ All labs have been updated to the latest software versions

Additional Information

Custom Stock Status No