Designing FPGAs Using the Vivado Design Suite 4 July 11-12, 2022 *Confirmed to run Online
Details
Learn how to use the advanced aspects of the Vivado® Design Suite and Xilinx hardware. The focus is on: ▪ Applying timing constraints for source-synchronous and system-synchronous interfaces ▪ Utilizing floorplanning techniques ▪ Employing advanced implementation options ▪ Utilizing Xilinx security features ▪ Identifying advanced FPGA configurations ▪ Debugging a design at the device startup phase ▪ Using Tcl scripting in non-project batch flows This is the final course in the Designing FPGAs Using the Vivado Design Suite series. What's New for 2021.2 ▪ All labs have been updated to the latest software versions
Additional Information
Custom Stock Status | No |
---|