Zynq UltraScale+MPSoC-Hardware Designer

This course provides hardware designers with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective. The emphasis is on: ▪ Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU) ▪ Reviewing the various power domains and their control structure ▪ Illustrating the processing system (PS) and programmable logic (PL) connectivity ▪ Utilizing QEMU to emulate hardware behavior What's New for 2021.2 ▪ All labs have been updated to the latest software versions.