Designing for CPLD Performance

Designing for Performance for CPLDs is an intermediate-level course that provides a comprehensive overview of the CPLD software flow. By applying the techniques presented in this course, you will be able to enhance design performance and make the best possible use of Xilinx CPLD architectures.

This course uses the ISE™ 9.1 software, including the Constraints Editor and Timing Analyzer. Other topics include understanding the CPLD logic engine, estimating power, and fitting difficult designs.