Event

Title:

Designing with the Versal ACAP: PCI Express System

Start date:

September 19

End date:

- September 20

Start time:

09:00 am

End time:

05:00 pm

Location:

Online

Registration:

Description:

Course Outline
Day 1

▪ Introduction to PCI Express
Introduces the course and discusses a few key topics of the PCI Express protocol. {Lecture, Lab}
▪ Versal ACAP PCIe Solutions Overview
Provides an overview of the Xilinx PCI Express solutions in the Versal architecture and identifies key differentiators. {Lecture}
▪ PCIe Block Architecture and Functionality
Describes the PL PCIe block architecture. You will learn details on the block features and functionality. {Lecture}
▪ PCIe Block Interfaces Overview
Provides an overview of the PL PCIe block interfaces. Deeper discussion on physical layer and general interfaces. {Lecture}
▪ PCIe Block Requester Interfaces
Reviews the requester AXI4-Streaming core interfaces. You will learn how to utilize packet descriptors for request interfaces. {Lecture}
▪ PCIe Block Completer Interfaces
Reviews the completer AXI4-Streaming core interfaces. You will learn how to utilize packet descriptors for completion interfaces. {Lecture, Lab}
▪ PCIe Block Customization
Illustrates customizing the PL PCIe block. You will learn how to utilize the various configuration options. {Lecture, Lab}
▪ PCIe Block Testbench and Simulation
Discusses PCIe block simulation. You will learn how to utilize the generated example design to verify the functionality of the PL PCIe solution. {Lecture, Lab}

Day 2

▪ PCIe Block Implementation
Discusses implementation topics. You will review the placement recommendations for the PL PCIe blocks, transceivers, clocks, and resets. {Lecture}
▪ PL PCIe Block Debugging Overview
Describes the PCI Express debugging options in the Versal ACAP PCI Express physical and transaction layers. You will learn how to perform PCI Express link debug. {Lecture}
▪ Introduction to DMA
Reviews DMA basics and describes DMA in the context of the PCI Express standard. {Lecture}
▪ PL PCIe XDMA-Bridge Subsystem
Describes the Xilinx XDMA architecture and features as well as DMA descriptor usage and interface options. You will learn how to utilize the Xilinx XDMA subsystem. {Lecture, Lab}
▪ PL PCIe QDMA Subsystem
Describes the Xilinx QDMA architecture and features. You will learn how to utilize the Xilinx QDMA subsystem and its queue usage. {Lecture}
▪ CPM4 Architecture and Functionality
Describes the CPM4 block architecture and functionality. You will learn the commonalities and differences to the PL PCIe solution. {Lecture}
▪ CPM Block Customization
Reviews the configuration options of the CIPS CPM block. You will learn how to customize the CPM PCIe block. {Lecture}
▪ CPM IP Use Cases
Describes typical use cases for the Versal ACAP PCI Express solutions to enable you to select the right solution for your design requirements. {Lecture, Lab}

Registration for this course is available through our Online Store.