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Event

Title: 
*Confirmed to run! Designing FPGAs Using Vivado Design Suite 4
Start date: 
July 11
End date: 
- July 12
Start time: 
09:00 am
End time: 
05:00 pm
Location: 
Online
Registration: 
Register online in our secure store
Description:


This course tackles the most sophisticated aspects of the Vivado Design Suite and Xilinx hardware. The course enables you to use the advanced capabilities of the Vivado Design Suite to achieve design closure.

After completing this comprehensive training, you will have the necessary skills to:

  • Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
  • Analyse a timing report to identify how to center the clock in the data eye
  • Use Tcl scripting in non-project batch flows to synthesize, implement, and generate custom timing reports
  • Utilize floorplanning techniques to improve design performance
  • Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
  • Utilize Xilinx security features, bitstream encryption, and authentification using AED for design and IP security
  • Identify advanced FPGA configurations, such as daisy chain and gangs, for configuring multiple FPGAs in a design
  • Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset.

Course Outline

Day 1

  • UltraFast Design Design Methodology Introduction 4 (Lecture)
  • Scripting in the Non-Project Batch Flow (Lecture,Lab)
  • Using Procedures and Lists in Scripting (lecture)
  • Using regexp in Tcl Scripting (Lecture,Lab)
  • I/O Timing Scenarios (Lecture)
  • Source-Synchronous I/O Timing (Lecture,Lab)
  • System-Synchronous I/O Timing (Lecture, Demo)
  • Modifying the Clock Edge for Hold Analysis in Multicycle Paths (Lecture,Demo)
  • Timing Constraints Priority (Lecture)
  • Daisy Chains and Gangs in Configuration (Lecture)
  • Managing Remote IP (Lecture,Lab)
  • Introduction to Floorplanning (Lecture)
  • Design Analysis and Floorplanning (Lecture,Lab)

Day 2

  • Incremental Compile Flow (Lecture,Lab)
  • Re-entrant Implementation Mode (Lecture,Lab)
  • Physical Optimization (Lecture,Lab)
  • Trigger and Debug at Device Startup (Lecture,Demo)
  • Scripting for a VLA Design (Lecture,Lab)
  • ILA Timing Recommendations (Lecture)
  • Debug Hub Core Timing Recommendations (Lecture)
  • Vivado design Suite Debug Methodology (Lecture)
  • Cross Triggering Multiple ILAs (Lecture,Lab)
  • Power Management Techniques (Lecture)
  • eFUSE for Bitstream Security (Lecture,Lab)

Topic Descriptions

Day 1

  • UltraFast Design Methodology Introduction 4-Introduces the methodology guidelines covered in this course.
  • Scripting in the Non-Project Batch Flow-Write Tcl commands in the non-project batch flow for a design.
  • Using Procedures and Lists in Scripting-Employ procedures and lists in Tcl scripting.
  • Using regexp in Tcl Scripting-Use regular expressions to find a pattern in a text file while scripting an action in the Vivado Design Suite.
  • I/O Timing Scenarios-Overview of various I/O timing scenarios, such as source and system synchronous, direct/MMCM capture, and edge/center aligned data.
  • Source-Synchronous I/O Timing-Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface.
  • System-Synchronous I/O timing-Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface.
  • Modifying the clock Edge for Hold Analysis in Multicycle Paths-Understand why the clock edge for hold analysis needs to be modified when a multi-cycle path constraint is applied.
  • Timing Constraints Priority-Identify the priority of timing constraints.
  • Daisy Chains and Gangs in Configuration-Introduces advanced configuration schemes for multiple FPGAs.
  • Managing Remote IP-Store IP and related files remote to the current working project directory.
  • Introduction to Floorplanning-Introduction to floorplannings and how to use pblocks while floorplanning.
  • Design Analysis and Floorplannings-Explore the pre- and [post-implementation design analysis features of the Vivado IDE.

Day 2

  • Incremental Compile Flow- utilize the incremental compile flow when making last-minute changes.
  • Re-entrant Implementation Mode- Use re-entrant mode on partial routed nets.
  • Physical Optimization-Use physical optimization techniques for timing closure.
  • Trigger and Debug at Device Startup-Debug the events around the device startup.
  • Scripting for a VLA Design-Use Tcl scripting for VLA designs for adding probes and making connections to probes.
  • ILA Timing Recommendations-Understand the impact of using ILA for design timing closure.
  • Debug Hub Core Timing Recommendations-Understand the impact of using the debug core hub in design timing closure.
  • Vivado Design Suite Debug Methodology-Employ the debug methodology for debugging a design using the Vivado logic analyzer.
  • Cross Triggering Multiple ILAs-Use the cross-triggering feature to trigger multiple ILA's.
  • Power Management Techniques-Identify techniques used for low power design.
  • eFUSE for Bitstream Security-Use eFUSE for bitstream security.

Register Today

Registration for this course is available through our Online Store.