Connect on LinkedIn
Connect on Facebook
Watch us on YouTube
Event
After completing this comprehensive training, you will have the
necessary skills to:
▪ Describe the Versal ACAP architecture at a high level
▪ Describe the various engines in the Versal ACP device
▪ Use the various blocks from the Versal architecture to create
complex systems
▪ Perform system-level simulation and debugging
▪ Identify and apply different design methodologies
Course Outline 2020.2
Day 1
▪ Introduction
Talks about the need for Versal devices and gives an overview of the different Versal families. {Lecture}
▪ Architecture Overview
Provides a high-level overview of the Versal architecture, illustrating the various engines available in the the Versal architecture. {Lecture}
▪ Design Tool Flow
Maps the various engines in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture, Lab}
▪ Adaptable Engines (PL)
Describes the logic resources available in the Adaptable Engine. {Lecture}
▪ Clocking Architecture
Discusses the clocking architecture, clock buffers, clock routing, clock management functions, and clock de-skew. {Lecture, Lab}
▪ SelectI/O Resources
Describes the I/O bank, SelectIO™ interface, and I/O delay features. {Lecture}
▪ Processing System
Reviews the Cortex™-A72 processor APU and Cortex-R5 processor RPU that form the Scalar Engine. The platform management controller (PMC), processing system manager
(PSM), I/O peripherals, and PS-PL interfaces are also covered. {Lecture}
▪ PMC, Boot, and Configuration
Describes the platform management controller, platform loader and manager (PLM) software and boot and configuration. {Lecture, Lab}
▪ System Interrupts
Discusses the different system interrupts and interrupt controllers. {Lecture}
Day 2
Timers, Counters, and RTC Provides an overview of timers and counters, including the system counter, triple timer counter (TTC), watchdog timer, and real-time clock (RTC). {Lecture}
▪ Software Build Flow
Provides an overview of the different build flows, such as the do it yourself, Yocto Project, and PetaLinux tool flows. {Lecture, Lab}
▪ Software Stack
Reviews the Versal ACAP bare-metal, FreeRTOS, and Linux software stack and their components. {Lecture}
▪ DSP Architecture
Describes the DSP58 slice and compares the DSP58 slice with the DSP48 slice. DSP58 modes are also covered in detail. {Lecture}
▪ Versal AI Engine
Discusses the AI Engine array architecture, terminology, and AIE interfaces. {Lecture}
▪ NoC Introduction and Concepts
Covers the reasons to use the network on chip, its basic elements, and common terminology. {Lecture, Lab}
▪ Device Memory
Describes the available memory resources, such as block RAM, UltraRAM, LUTRAM, embedded memory, OCM, and DDR. The integrated memory controllers are also covered. {Lecture}
▪ Programming Interfaces
Reviews the various programming interfaces in the Versal ACAP. {Lecture}
▪ Versal Application Partitioning
Covers what application partitioning is and how the mapping of resources based on the models of computation can be performed. {Lecture}
Day 3
▪ CCIX and PCIe Module (CPM)
Provides an overview of the CCIX PCIe module and describes the PL and CPM PCIe blocks. {Lecture}
▪ Transceivers
Describes the transceivers in the Versal ACAP. {Lecture}
▪ Power, Thermal, and PCB
Discusses the power domains in the Versal ACAP as well as power optimization and analysis techniques. Thermal design challenges are also covered. {Lecture}
▪ Debugging
Covers the Versal ACAP debug interfaces, such as the test
access port (TAP), debug access port (DAP) controller, and
high-speed debug port (HSDP). {Lecture, Lab}
▪ Security Features
Describes the security features of the Versal ACAP. {Lecture}
▪ System Simulation
Explains how to perform system-level simulation in a Versal ACAP design. {Lecture, Lab}
▪ System Design Methodology
Reviews the Xilinx methodology for designing a system. {Lecture}
Register Today
Registration for this course is available through our Online Store.