Course Calendar

BEGIN:VCALENDAR VERSION:2.0 PRODID:-//TYPO3/NONSGML Calendar Base (cal) V1.3.3//EN METHOD:PUBLISH could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1124 DTSTAMP:20200120T172827 DTSTART:20200203T100000Z DTEND:20200203T120000Z CATEGORIES:Vivado, Languages, General, Connectivity SUMMARY:Lunch-N-Learn DESCRIPTION:Lunch-N-Learn Information and registration link on PDF Flyer "CLICK HERE"\n\n\n\n LOCATION:Online END:VEVENT BEGIN:VEVENT UID:_1_1040 DTSTAMP:20180626T164321 DTSTART:20200207T100000Z DTEND:20200207T120000Z CATEGORIES:Vivado, Languages, General, Connectivity SUMMARY:Lunch-N-Learn DESCRIPTION:Lunch-N-Learn Information and registration link on PDF Flyer "CLICK HERE"\n\n\n\n LOCATION:Online END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1131 DTSTAMP:20200220T191737 DTSTART:20201204T090000Z DTEND:20201204T170000Z CATEGORIES:Embedded Design SUMMARY:Migrating to Vitis Embedded Software Development IDE DESCRIPTION:After completing this comprehensive training, you will have thenecessary skills to:▪ Develop and deploy an application on a Xilinx embedded systemusing the Vitis unified software platform▪ Migrate an existing SDK project to the Vitis platform\n\n\n\nCourse Outline\n\nOverview of Embedded Software DevelopmentOverview of the process for building a user application. {Lecture}▪ Driving the Vitis Software Development ToolIntroduces the basic behaviors required to drive the Vitis tool togenerate a debuggable C/C++ application. {Lecture, Lab}▪ Migrating from SDK to the Vitis PlatformOverview of migrating existing Xilinx SDK projects to Vitissoftware development projects {Lecture, Demo}▪ Standalone Software Platform Development and CodingSupportCovers the various software components, or layers, supplied byXilinx that aid in the creation of low-level software. Also the basicservices (libraries) available. {Lecture, Lab}▪ Linux Software Application Development OverviewHighlights important parts of the underlying Linux system as itpertains to applications. {Lecture}▪ Building a Linux Application in the Vitis IDEReviews the use of the Vitis tool for Linux software development.{Lecture, Lab}▪ System DebuggerDescribes the basics of actually running a debugger andillustrates the most commonly used debugging commands.{Lecture, Lab}▪ Profiling OverviewIntroduces the purpose and techniques for profiling a userapplication. {Lecture, Lab}\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPDF version of this page.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1174 DTSTAMP:20201228T175418 DTSTART:20210114T090000Z DTEND:20210114T170000Z CATEGORIES:Embedded Design SUMMARY:Designing with the Versal ACAP: NoC DESCRIPTION:This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.The emphasis of this course is on:▪ Enumerating the major components comprising the NoC architecture in the Versal ACAP▪ Implementing a basic design using the NoC▪ Configuring the NoC for efficient data movement\n\nCourse Outline 2020.2Day 1\n\nArchitecture Overview for Existing Xilinx UsersIntroduces to students that already have familiarity with Xilinx architectures to the new and updated features found in the Versal ACAP devices. {Lecture}▪ Versal ACAPs Compared to Zynq UltraScale+ DevicesThe Versal ACAP has a number of similarities to the Zynq® UltraScale+™ MPSoC devices. Understanding what is the same, what is different, and what is brand new helps put this powerful new part into context. {Lecture}▪ NoC Introduction and ConceptsReviews the basic vocabulary and high-level operations of the NoC. {Lecture, Lab}▪ NoC ArchitectureProvides the first deep dive into the sub-blocks of the NoC andhow they are used. Describes how the NoC is accessed from the programmable logic. {Lecture}▪ Design Tool Flow OverviewDesigners come to the Versal ACAP devices with different goals. This module explores how traditional FPGA designers, embedded developers, and accelerated system designers would use the various tools available in the Xilinx toolbox. {Lecture}▪ NoC DDR Memory ControllerThe integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC's DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use. {Lecture}▪ NoC Performance TuningSynthesizes everything about the NoC and its DDRMCs, illustrating how to fine tune the NoC for the best performance. {Lecture, Lab}▪ System Design MigrationDescribes how different users will leverage tools and processes to migrate their designs to the Versal ACAP devices. {Lecture}\n\nPDF course description\n\nRegister Today\n\nRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1179 DTSTAMP:20210402T171352 DTSTART:20210602T090000Z DTEND:20210602T170000Z CATEGORIES:Embedded Design SUMMARY:*Confirmed to run! Designing with the Versal ACAP: NoC DESCRIPTION:This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.The emphasis of this course is on:▪ Enumerating the major components comprising the NoC architecture in the Versal ACAP▪ Implementing a basic design using the NoC▪ Configuring the NoC for efficient data movement\n\nCourse Outline 2020.2Day 1\n\nArchitecture Overview for Existing Xilinx UsersIntroduces to students that already have familiarity with Xilinx architectures to the new and updated features found in the Versal ACAP devices. {Lecture}▪ Versal ACAPs Compared to Zynq UltraScale+ DevicesThe Versal ACAP has a number of similarities to the Zynq® UltraScale+™ MPSoC devices. Understanding what is the same, what is different, and what is brand new helps put this powerful new part into context. {Lecture}▪ NoC Introduction and ConceptsReviews the basic vocabulary and high-level operations of the NoC. {Lecture, Lab}▪ NoC ArchitectureProvides the first deep dive into the sub-blocks of the NoC andhow they are used. Describes how the NoC is accessed from the programmable logic. {Lecture}▪ Design Tool Flow OverviewDesigners come to the Versal ACAP devices with different goals. This module explores how traditional FPGA designers, embedded developers, and accelerated system designers would use the various tools available in the Xilinx toolbox. {Lecture}▪ NoC DDR Memory ControllerThe integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC's DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use. {Lecture}▪ NoC Performance TuningSynthesizes everything about the NoC and its DDRMCs, illustrating how to fine tune the NoC for the best performance. {Lecture, Lab}▪ System Design MigrationDescribes how different users will leverage tools and processes to migrate their designs to the Versal ACAP devices. {Lecture}\n\nPDF course description\n\nRegister Today\n\nRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1172 DTSTAMP:20201204T193625 DTSTART:20210823T090000Z DTEND:20210823T170000Z CATEGORIES:Embedded Design SUMMARY:*Confirmed to run! Designing w/the Versal ACAP: Power & Board Design DESCRIPTION:This course provides a system-level understanding of power and thermal issues related to designing with the Versal™ ACAP.The emphasis of this course is on:▪ Estimating power using power analysis▪ Managing thermal design ▪ Understanding Versal device packaging▪ Using the Versal PCB Schematic Checklist for accelerating PCB designCourse Outline 2020.2Day 1\n\n▪ Versal ACAP Architecture Overview for Existing Xilinx UsersIntroduces to students that already have familiarity with Xilinx architectures the new and updated features found in the Versal ACAP devices. {Lecture}▪ Power and Thermal Solutions OverviewIntroduces key power and thermal concepts and explores some of capabilities of the Versal ACAP devices and introduces the power distribution network flow. {Lecture, Lab, Demo}▪ Packaging and Power IntegrityDescribes key elements when modeling a PDN and dives deeper into packaging considerations. {Lecture}▪ Power ManagementDiscusses power domains and how they can be controlled along with basic techniques used to lower overall power consumption. {Lecture}▪ Power Supply BackgrounderReviews linear and switching power supplies and common terms used to specify power supply characteristics. {Lecture}▪ Designing the Power SupplyConsolidates the thermal management concepts of the course for achieving a successful design. {Lecture}▪ PCB Design Verification – Versal ACAP Schematic ChecklistReviews PCB design verification using the Schematic Checklist. {Lecture, Lab}\n\n\n\nRegister Today\n\nRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1196 DTSTAMP:20211026T155951 DTSTART:20211117T090000Z DTEND:20211117T093000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Designing w/FPGAs w/Vivado Design 1 & 2 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1204 DTSTAMP:20211026T161757 DTSTART:20211117T133000Z DTEND:20211117T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Designing w/FPGAs w/Vivado Design 3 & 4 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1194 DTSTAMP:20211026T155934 DTSTART:20211118T090000Z DTEND:20211118T093000Z CATEGORIES:Embedded Design SUMMARY:*PStack: HLS C/C++Vitis & Vivado DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1206 DTSTAMP:20211026T162115 DTSTART:20211118T133000Z DTEND:20211118T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Versal:ACAP AI Engine 1,2,3 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1207 DTSTAMP:20211026T162306 DTSTART:20211119T090000Z DTEND:20211119T093000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Zynq US+ MPSoC (Hardware/Software) DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1192 DTSTAMP:20211025T203110 DTSTART:20211119T133000Z DTEND:20211119T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Versal:ACAP Architecture & Methodology DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1200 DTSTAMP:20211026T161326 DTSTART:20211215T090000Z DTEND:20211215T093000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Designing w/FPGAs w/Vivado Design 1 & 2 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1198 DTSTAMP:20211026T155955 DTSTART:20211215T133000Z DTEND:20211215T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Designing w/FPGAs w/Vivado Design 3 & 4 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1202 DTSTAMP:20211026T161526 DTSTART:20211216T090000Z DTEND:20211216T093000Z CATEGORIES:Embedded Design SUMMARY:*PStack: HLS C/C++Vitis & Vivado DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1205 DTSTAMP:20211026T162111 DTSTART:20211216T133000Z DTEND:20211216T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Versal:ACAP AI Engine 1,2,3 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1197 DTSTAMP:20211026T155953 DTSTART:20211217T090000Z DTEND:20211217T093000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Zynq US+ MPSoC (Hardware/Software) DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1210 DTSTAMP:20211026T162515 DTSTART:20211217T133000Z DTEND:20211217T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Versal:ACAP Architecture & Methodology DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1199 DTSTAMP:20211026T161313 DTSTART:20220112T090000Z DTEND:20220112T130000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Designing w/FPGAs w/Vivado Design 1 & 2 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1203 DTSTAMP:20211026T161754 DTSTART:20220112T133000Z DTEND:20220112T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Designing w/FPGAs w/Vivado Design 3 & 4 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1201 DTSTAMP:20211026T161521 DTSTART:20220113T090000Z DTEND:20220113T130000Z CATEGORIES:Embedded Design SUMMARY:*PStack: HLS C/C++Vitis & Vivado DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1195 DTSTAMP:20211026T155948 DTSTART:20220113T133000Z DTEND:20220113T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Versal:ACAP AI Engine 1,2,3 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1208 DTSTAMP:20211026T162310 DTSTART:20220114T090000Z DTEND:20220114T130000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Zynq US+ MPSoC (Hardware/Software) DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1209 DTSTAMP:20211026T162512 DTSTART:20220114T133000Z DTEND:20220114T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Versal:ACAP Architecture & Methodology DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1188 DTSTAMP:20211015T154753 DTSTART:20220202T090000Z DTEND:20220202T170000Z CATEGORIES:Embedded Design SUMMARY:Migrating to Vitis Embedded Software Development IDE DESCRIPTION:After completing this comprehensive training, you will have thenecessary skills to:▪ Develop and deploy an application on a Xilinx embedded systemusing the Vitis unified software platform▪ Migrate an existing SDK project to the Vitis platform\n\n\n\nCourse Outline 2020.2\n\nOverview of Embedded Software DevelopmentOverview of the process for building a user application. {Lecture}▪ Driving the Vitis Software Development ToolIntroduces the basic behaviors required to drive the Vitis tool to generate a debuggable C/C++ application. {Lecture, Lab}▪ Migrating from SDK to the Vitis PlatformOverview of migrating existing Xilinx SDK projects to Vitis software development projects {Lecture, Demo}▪ Standalone Software Platform Development and Coding SupportCovers the various software components, or layers, supplied by Xilinx that aid in the creation of low-level software. Also the basic services (libraries) available.{Lecture, Lab}▪ Linux Software Application Development OverviewHighlights important parts of the underlying Linux system as it pertains to applications. {Lecture}▪ Building a Linux Application in the Vitis IDEReviews the use of the Vitis tool for Linux software development. {Lecture, Lab}▪ System DebuggerDescribes the basics of actually running a debugger and illustrates the most commonly used debugging commands. {Lecture, Lab}▪ Profiling OverviewIntroduces the purpose and techniques for profiling a user application. {Lecture, Lab}\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1187 DTSTAMP:20210916T154239 DTSTART:20220218T090000Z DTEND:20220218T170000Z CATEGORIES:Embedded Design SUMMARY:Designing with the IP Integrator Tool DESCRIPTION:After completing this comprehensive training, you will have the necessary skills to:▪ Describe the Vivado tool flow for RTL-based and IP-based design flows▪ Create a Vivado IP integrator block design using the Vivado Design Suite▪ Describe the block design container feature in the IP integrator▪ Package custom IP and add it to the IP catalog repository or manage it in a remote location▪ Use the IP integrator to add and configure the Versal ACAP CIPS block and export the generated hardware▪ Configure the AXI NoC to access DDR memory controllers in Versal ACAP devices▪ Use a revision control system in the Vivado Design Suite flows▪ Use the IP integrator to add debug cores to an existing block design to debug the designCourse Outline\n\nVivado IP Catalog▪ Vivado IP FlowCustomize IP, instantiate IP, and verify the hierarchy of your design IP. {Lecture, Demo}IP Integrator▪ Designing with the IP IntegratorUse the Vivado IP integrator to create the uart_led subsystem. {Lecture, Demo, Lab}▪ Block Design Containers in the Vivado IP Integrator Describes the block design container (BDC) feature and shows how to create a BDC in the IP integrator. {Lecture}▪ Creating and Packaging Custom IPCreate your own IP and package and include it in the Vivado IP catalog. {Lecture, Lab}▪ Versal ACAP: Hardware Platform Development Using the Vivado IP Integrator Describes the different Versal ACAP design flows and covers the platform creation process using the Vivado IP integrator. {Lecture, Lab}▪ Versal ACAP: NoC Introduction and ConceptsReviews the basic vocabulary and high-level operations of the NoC. {Lecture, Lab}Debugging▪ Debug Flow in an IP Integrator Block DesignInsert the debug cores into IP integrator block designs. {Lecture, Lab}Version Control Systems▪ Revision Control Systems in the Vivado Design SuiteUse version control systems with Vivado design flows. {Lecture}Vivado IP Catalog▪ Managing IP in Remote LocationsStore IP and related files remote to the current working project directory. {Lecture}\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1132 DTSTAMP:20200220T191742 DTSTART:20220307T090000Z DTEND:20220307T170000Z CATEGORIES:Embedded Design SUMMARY:Using Xilinx Alveo Cards to Accelerate Dynamic Workloads DESCRIPTION:After completing this comprehensive training, you will have the necessary skills to:▪ Describe the Alveo Data Center accelerator cards and list the advantages of these cards and the available software solutions stack▪ Explain how the Vitis unified software platform helps software developers to focus on applications▪ Describe the elements of the development flow, such as software emulation, hardware emulation, and system run as well as debugging support for the host code and kernel code▪ Describe the partner solutions available in the cloud and on premises for the Alveo Data Center accelerator cards\n\nCourse Outline▪ Alveo Data Center Accelerator Cards OverviewDescribes the Alveo Data Center accelerator cards and lists the advantages of these cards and the available software solutions stack. {Lecture}▪ Getting Started with Alveo Data Center Accelerator CardsDescribes the hardware and software installation procedures for the Alveo Data Center accelerator cards. {Lecture}▪ Introduction to the Vitis Unified Software PlatformExplains how software/hardware engineers and application developers can benefit from the Vitis unified software environment and OpenCL framework. {Lecture}▪ Vitis IDE Tool OverviewDescribes the elements of the development flow, such as software emulation, hardware emulation, and system run as well as debugging support for the host code and kernel code. {Lecture}▪ Alveo Accelerator Card Ecosystem Partner SolutionsDescribes the partner solutions available in the cloud and on premises for Alveo Data Center accelerator cards. {Lecture}▪ Xilinx Real-Time Video Server Appliance (Optional)Describes the Xilinx Real-Time Video Server appliance reference architectures, the optimized software solution stack for video applications, and various features offered by Alveo card live transcoding. {Lecture}\n\nPDF Version\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1223 DTSTAMP:20220104T175709 DTSTART:20220308T090000Z DTEND:20220308T170000Z CATEGORIES:Embedded Design SUMMARY:Kria KV260 Vision AI Starter Kit & Som DESCRIPTION:After completing this comprehensive training, you will have the necessary skills to:\n\n▪ Describe the Kria K26 SOM and its advantages▪ Describe the features and capabilities of the KV260 Vision AI Starter Kit carrier card▪ Get started with the Vision AI Starter Kit▪ Deploy vision-based applications, such as the Smart Camera, AI Box, Defect Detection, and NLP SmartVision applications, using the kit▪ Build the hardware and software design components from scratch ▪ Customize the AI models used in the applications▪ Design your own carrier card\n\nCourse Outline ▪ Xilinx Kria System-on-Module (SOM) OverviewIntroduces the Xilinx Kria K26 SOM and describes its advantages. Also outlines the features, functional interfaces, mechanical, and thermal aspects of the SOM. {Lecture}▪ Xilinx Kria KV260 Vision AI Starter Kit OverviewProvides an overview of the Xilinx Kria KV260 Vision AI Starter Kit, its features, and interfaces. The boot devices, heat sink, frmware, and power-on sequence for the kit are also described. {Lecture}▪ Getting Started with the Vision AI Starter Kit Covers how the initial board setup looks like and how to set up the SD card, make the necessary connections with the kit, and boot the kit. Also shows how to use the platform management utility to install, select, and deploy different applications. {Lecture, Demos}▪ Introduction to Vitis Video Analytics SDK (VVAS)Provides an overview of the Vitis Video Analytics SDK (VVAS) technology and its core components. {Lecture}▪ Accelerating Applications with the KV260 Vision AI Starter KitDescribes the top-level block diagram and pipeline stages for different accelerated applications, such as the Smart Camera, AI Box, Defect Detection, NLP SmartVision applications. Also demonstrates how to deploy these applications using the KV260 Starter Kit. {Lecture, Demos, Labs}Note: For instructor-led training, the "Running the Demo Application with the Kria KV260 Starter Kit" lab is optional.▪ Building the Hardware and Software Design ComponentsIllustrates how the hardware and software design components are built from scratch for an accelerated application. {Lecture, Lab}▪ Customizing the AI ModelsShows how to customize the AI models used in the accelerated applications. {Lecture}▪ Kria SOM Carrier Card Design GuideOutlines the electrical, mechanical, firmware, thermal, and power-on configuration design considerations that must be addressed as part of designing a Xilinx SOM-compatible carrier card. {Lecture}\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1222 DTSTAMP:20211109T172036 DTSTART:20220318T090000Z DTEND:20220318T170000Z CATEGORIES:Embedded Design SUMMARY:Migrating from ISE & Spartan 6 to Vivado & 7 Series DESCRIPTION:After completing this comprehensive training, you will have the necessary skills to:\n\n▪ Analyze Spartan-6 designs and identify the critical parts of the design and how to update them for newer Xilinx devices▪ Migrate to new clocking, IO, and other key resources▪ Rewrite UCF constraints using the new XDC format▪ Use the Xilinx Baselining method to close timing▪ Use the new Vivado IP Catalog to instantiate IP\n\nCourse Outline▪ ISE versus Vivado Design Flow▪ Vivado Design Suite Project Mode▪ Clocking Resource Migration▪ I/O Resource Migration▪ UCF to XDC Constraints▪ LAB/Demo: Vivado XDC Constraints Editor▪ CoreGen to Vivado IP Catalog▪ Lab/Demo: IP Flow▪ Vivado Timing Reports▪ Baselining Approach to Timing Closure\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1129 DTSTAMP:20200130T174103 DTSTART:20220325T090000Z DTEND:20220325T170000Z CATEGORIES:Embedded Design SUMMARY:(Workshop) Embedded & Accelerating Applications w/Vitis Unified Software DESCRIPTION:After completing this comprehensive training, you will have thenecessary skills to:\n\n\n\n▪ Implement an effective software design environment for a Xilinx embedded system using the Vitis unified software platform▪ Write a basic user application and run it on an embedded system platform▪ Describe how the FPGA architecture lends itself to parallel computing▪ Explain how the Vitis unified software environment helps software developers to focus on applications▪ Create kernels from C, C++, or RTL IP using the RTL Kernel Wizard▪ Profile the design using Vitis\n\n\n\nCourse Outline\n\n\n\n▪ Introduction to the Vitis Unified Software Platform▪ Vitis IDE Tool Overview▪ Migrating Xilinx SDK Projects to the Vitis Platform▪ Driving the Vitis Software Development Tool▪ Introduction to Hardware Acceleration▪ Alveo Data Center Accelerator Cards Overview▪ Introduction to the Nimbix Cloud▪ Profiling▪ Debugging▪ Introduction to C/C++ based Kernels▪ Using the RTL Kernel Wizard to Reuse Existing IP asAccelerators▪ Vitis Accelerated Libraries\n\n\n\nPDF version of this page.\n\nRegister TodayRegistration for this course is available through our Online Store.\n\n LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl END:VCALENDAR

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes that are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.

Student Cancellation Policy

Student cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.

Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.

Student cancellations must be sent to registrar(at)fastertechnology.com

Faster Technology Course Cancellation Policy

Due to low class size and other certain considerations, Faster Technology may cancel a class up to 7 days before the scheduled start date of the class.  In such cases, all students will be entitled to a 100% refund.  Faster Technology will notify registered students of "at risk" classes prior to cancellation.

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Under no circumstances is Faster Technology responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.