Course Calendar

BEGIN:VCALENDAR VERSION:2.0 PRODID:-//TYPO3/NONSGML Calendar Base (cal) V1.3.3//EN METHOD:PUBLISH could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1124 DTSTAMP:20200120T172827 DTSTART:20200203T100000Z DTEND:20200203T120000Z CATEGORIES:Vivado, Languages, General, Connectivity SUMMARY:Lunch-N-Learn DESCRIPTION:Lunch-N-Learn Information and registration link on PDF Flyer "CLICK HERE"\n\n\n\n LOCATION:Online END:VEVENT BEGIN:VEVENT UID:_1_1040 DTSTAMP:20180626T164321 DTSTART:20200207T100000Z DTEND:20200207T120000Z CATEGORIES:Vivado, Languages, General, Connectivity SUMMARY:Lunch-N-Learn DESCRIPTION:Lunch-N-Learn Information and registration link on PDF Flyer "CLICK HERE"\n\n\n\n LOCATION:Online END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1131 DTSTAMP:20200220T191737 DTSTART:20201204T090000Z DTEND:20201204T170000Z CATEGORIES:Embedded Design SUMMARY:Migrating to Vitis Embedded Software Development IDE DESCRIPTION:After completing this comprehensive training, you will have thenecessary skills to:▪ Develop and deploy an application on a Xilinx embedded systemusing the Vitis unified software platform▪ Migrate an existing SDK project to the Vitis platform\n\n\n\nCourse Outline\n\nOverview of Embedded Software DevelopmentOverview of the process for building a user application. {Lecture}▪ Driving the Vitis Software Development ToolIntroduces the basic behaviors required to drive the Vitis tool togenerate a debuggable C/C++ application. {Lecture, Lab}▪ Migrating from SDK to the Vitis PlatformOverview of migrating existing Xilinx SDK projects to Vitissoftware development projects {Lecture, Demo}▪ Standalone Software Platform Development and CodingSupportCovers the various software components, or layers, supplied byXilinx that aid in the creation of low-level software. Also the basicservices (libraries) available. {Lecture, Lab}▪ Linux Software Application Development OverviewHighlights important parts of the underlying Linux system as itpertains to applications. {Lecture}▪ Building a Linux Application in the Vitis IDEReviews the use of the Vitis tool for Linux software development.{Lecture, Lab}▪ System DebuggerDescribes the basics of actually running a debugger andillustrates the most commonly used debugging commands.{Lecture, Lab}▪ Profiling OverviewIntroduces the purpose and techniques for profiling a userapplication. {Lecture, Lab}\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPDF version of this page.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1174 DTSTAMP:20201228T175418 DTSTART:20210114T090000Z DTEND:20210114T170000Z CATEGORIES:Embedded Design SUMMARY:Designing with the Versal ACAP: NoC DESCRIPTION:This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.The emphasis of this course is on:▪ Enumerating the major components comprising the NoC architecture in the Versal ACAP▪ Implementing a basic design using the NoC▪ Configuring the NoC for efficient data movement\n\nCourse Outline 2020.2Day 1\n\nArchitecture Overview for Existing Xilinx UsersIntroduces to students that already have familiarity with Xilinx architectures to the new and updated features found in the Versal ACAP devices. {Lecture}▪ Versal ACAPs Compared to Zynq UltraScale+ DevicesThe Versal ACAP has a number of similarities to the Zynq® UltraScale+™ MPSoC devices. Understanding what is the same, what is different, and what is brand new helps put this powerful new part into context. {Lecture}▪ NoC Introduction and ConceptsReviews the basic vocabulary and high-level operations of the NoC. {Lecture, Lab}▪ NoC ArchitectureProvides the first deep dive into the sub-blocks of the NoC andhow they are used. Describes how the NoC is accessed from the programmable logic. {Lecture}▪ Design Tool Flow OverviewDesigners come to the Versal ACAP devices with different goals. This module explores how traditional FPGA designers, embedded developers, and accelerated system designers would use the various tools available in the Xilinx toolbox. {Lecture}▪ NoC DDR Memory ControllerThe integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC's DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use. {Lecture}▪ NoC Performance TuningSynthesizes everything about the NoC and its DDRMCs, illustrating how to fine tune the NoC for the best performance. {Lecture, Lab}▪ System Design MigrationDescribes how different users will leverage tools and processes to migrate their designs to the Versal ACAP devices. {Lecture}\n\nPDF course description\n\nRegister Today\n\nRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1179 DTSTAMP:20210402T171352 DTSTART:20210602T090000Z DTEND:20210602T170000Z CATEGORIES:Embedded Design SUMMARY:*Confirmed to run! Designing with the Versal ACAP: NoC DESCRIPTION:This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.The emphasis of this course is on:▪ Enumerating the major components comprising the NoC architecture in the Versal ACAP▪ Implementing a basic design using the NoC▪ Configuring the NoC for efficient data movement\n\nCourse Outline 2020.2Day 1\n\nArchitecture Overview for Existing Xilinx UsersIntroduces to students that already have familiarity with Xilinx architectures to the new and updated features found in the Versal ACAP devices. {Lecture}▪ Versal ACAPs Compared to Zynq UltraScale+ DevicesThe Versal ACAP has a number of similarities to the Zynq® UltraScale+™ MPSoC devices. Understanding what is the same, what is different, and what is brand new helps put this powerful new part into context. {Lecture}▪ NoC Introduction and ConceptsReviews the basic vocabulary and high-level operations of the NoC. {Lecture, Lab}▪ NoC ArchitectureProvides the first deep dive into the sub-blocks of the NoC andhow they are used. Describes how the NoC is accessed from the programmable logic. {Lecture}▪ Design Tool Flow OverviewDesigners come to the Versal ACAP devices with different goals. This module explores how traditional FPGA designers, embedded developers, and accelerated system designers would use the various tools available in the Xilinx toolbox. {Lecture}▪ NoC DDR Memory ControllerThe integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC's DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use. {Lecture}▪ NoC Performance TuningSynthesizes everything about the NoC and its DDRMCs, illustrating how to fine tune the NoC for the best performance. {Lecture, Lab}▪ System Design MigrationDescribes how different users will leverage tools and processes to migrate their designs to the Versal ACAP devices. {Lecture}\n\nPDF course description\n\nRegister Today\n\nRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1172 DTSTAMP:20201204T193625 DTSTART:20210823T090000Z DTEND:20210823T170000Z CATEGORIES:Embedded Design SUMMARY:*Confirmed to run! Designing w/the Versal ACAP: Power & Board Design DESCRIPTION:This course provides a system-level understanding of power and thermal issues related to designing with the Versal™ ACAP.The emphasis of this course is on:▪ Estimating power using power analysis▪ Managing thermal design ▪ Understanding Versal device packaging▪ Using the Versal PCB Schematic Checklist for accelerating PCB designCourse Outline 2020.2Day 1\n\n▪ Versal ACAP Architecture Overview for Existing Xilinx UsersIntroduces to students that already have familiarity with Xilinx architectures the new and updated features found in the Versal ACAP devices. {Lecture}▪ Power and Thermal Solutions OverviewIntroduces key power and thermal concepts and explores some of capabilities of the Versal ACAP devices and introduces the power distribution network flow. {Lecture, Lab, Demo}▪ Packaging and Power IntegrityDescribes key elements when modeling a PDN and dives deeper into packaging considerations. {Lecture}▪ Power ManagementDiscusses power domains and how they can be controlled along with basic techniques used to lower overall power consumption. {Lecture}▪ Power Supply BackgrounderReviews linear and switching power supplies and common terms used to specify power supply characteristics. {Lecture}▪ Designing the Power SupplyConsolidates the thermal management concepts of the course for achieving a successful design. {Lecture}▪ PCB Design Verification – Versal ACAP Schematic ChecklistReviews PCB design verification using the Schematic Checklist. {Lecture, Lab}\n\n\n\nRegister Today\n\nRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1196 DTSTAMP:20211026T155951 DTSTART:20211117T090000Z DTEND:20211117T093000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Designing w/FPGAs w/Vivado Design 1 & 2 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1204 DTSTAMP:20211026T161757 DTSTART:20211117T133000Z DTEND:20211117T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Designing w/FPGAs w/Vivado Design 3 & 4 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1194 DTSTAMP:20211026T155934 DTSTART:20211118T090000Z DTEND:20211118T093000Z CATEGORIES:Embedded Design SUMMARY:*PStack: HLS C/C++Vitis & Vivado DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1206 DTSTAMP:20211026T162115 DTSTART:20211118T133000Z DTEND:20211118T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Versal:ACAP AI Engine 1,2,3 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1207 DTSTAMP:20211026T162306 DTSTART:20211119T090000Z DTEND:20211119T093000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Zynq US+ MPSoC (Hardware/Software) DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1192 DTSTAMP:20211025T203110 DTSTART:20211119T133000Z DTEND:20211119T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Versal:ACAP Architecture & Methodology DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1200 DTSTAMP:20211026T161326 DTSTART:20211215T090000Z DTEND:20211215T093000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Designing w/FPGAs w/Vivado Design 1 & 2 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1198 DTSTAMP:20211026T155955 DTSTART:20211215T133000Z DTEND:20211215T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Designing w/FPGAs w/Vivado Design 3 & 4 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1202 DTSTAMP:20211026T161526 DTSTART:20211216T090000Z DTEND:20211216T093000Z CATEGORIES:Embedded Design SUMMARY:*PStack: HLS C/C++Vitis & Vivado DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1205 DTSTAMP:20211026T162111 DTSTART:20211216T133000Z DTEND:20211216T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Versal:ACAP AI Engine 1,2,3 DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1197 DTSTAMP:20211026T155953 DTSTART:20211217T090000Z DTEND:20211217T093000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Zynq US+ MPSoC (Hardware/Software) DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1210 DTSTAMP:20211026T162515 DTSTART:20211217T133000Z DTEND:20211217T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Versal:ACAP Architecture & Methodology DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1208 DTSTAMP:20211026T162310 DTSTART:20220114T090000Z DTEND:20220114T130000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Zynq US+ MPSoC (Hardware/Software) DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_1209 DTSTAMP:20211026T162512 DTSTART:20220114T133000Z DTEND:20220114T173000Z CATEGORIES:Embedded Design SUMMARY:*PStack: Versal:ACAP Architecture & Methodology DESCRIPTION:Proficiency Stack Course Details\n\n4 hours $600 or 6 Training Credits\n\n\n\nYou can have both the flexibility of On-Demand, with the expertise and interaction of Instructor-Led Xilinx training.\n\nWe are pleased to announce the “Proficiency Stack”. This structured training solution combines self paced, on-demand content, with course-specific 4-hr “Applied Learning Lab(s)” @ 4-week intervals\n\nThe Lab is led by a certified Xilinx training professional.\n\nYou gain the following:\n\n1. Your individual questions are answered in a real-time, interactive format.\n\n2. You get additional tips, demos, techniques, “best-practices” and FPGA design insights.\n\n3. The value and application of your prior on-demand study is greatly enhanced.\n\n4. Timely follow-up to your selfpaced learning experience, maximizing productivity.\n\nThe Proficiency Stack is ideal for:\n\n1. New XPA and On-Demand Training Purchases.\n\n2. Customers having taken prior on-demand training\n\n3. Any customer wanting the benefit of concise expert instruction and interaction.\n\n "Applied Learning Labs" are 4 hours each and compliment the OnDemand courses. The OnDemand is not live or interactive, but when you attend the "Applied Learning Lab", a student can watch a live deep dive lab, explanation, techniques or ask specific questions from the OnDemand video\n\n "Applied Learning Lab" Description\n\nEach 4-hour lab is an interactive follow-up to on-demand content. \n\nEach lab session is structured to maximize customer engagement.\n\n5-minute welcome, establish basic rules to maximize interaction30-45 minutes open Q&A (customer driven, informal customer polling*)* Poll attendees on the initial experience with On-Demand content, determine focus areas/topics for “Applied Learning Lab” 60 minute Lab1 deep dive demo, explanation, techniques, best practices (Selected lab from course)15 minute break60 minute Lab2 deep dive demo, explanation, techniques, best practices ( Or deep dive into a particular topic from the class, can also be customer driven.45 minute presentation and review of key slides and take-aways from course PPT10 minute open Q&A Please come prepared to ask questions that facilitate your complete understanding and application of the on-demand content.\n\nIn addition, the certified Xilinx instructor will offer other tips, techniques and "Best Practices" for FPGA design. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1225 DTSTAMP:20220309T184534 DTSTART:20220318T090000Z DTEND:20220318T170000Z CATEGORIES:Embedded Design SUMMARY:Confirmed to run Free Workshop! Migrating from ISE & Spartan 6 to Vivado & 7 Series DESCRIPTION:After completing this comprehensive training, you will have the necessary skills to:\n\n▪ Analyze Spartan-6 designs and identify the critical parts of the design and how to update them for newer Xilinx devices▪ Migrate to new clocking, IO, and other key resources▪ Rewrite UCF constraints using the new XDC format▪ Use the Xilinx Baselining method to close timing▪ Use the new Vivado IP Catalog to instantiate IP\n\nCourse Outline▪ ISE versus Vivado Design Flow▪ Vivado Design Suite Project Mode▪ Clocking Resource Migration▪ I/O Resource Migration▪ UCF to XDC Constraints▪ LAB/Demo: Vivado XDC Constraints Editor▪ CoreGen to Vivado IP Catalog▪ Lab/Demo: IP Flow▪ Vivado Timing Reports▪ Baselining Approach to Timing Closure\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl BEGIN:VEVENT UID:_1_1228 DTSTAMP:20220715T183125 DTSTART:20220801T100000Z DTEND:20220801T170000Z CATEGORIES:Embedded Design SUMMARY:*FREE Workshop! Vitis and PetaLinux DESCRIPTION:After completing this workshop, you will have the necessary skills to:▪ Create an extensible platform using Vivado IPI▪ Export platform via XSA to PetaLinux▪ Export platform via XSA to Vitis▪ Describe the role of the Vitis HLS tools and design flow▪ Use PetaLinux tools and flow to refine OS▪ Build system level application incorporating PS and PL▪ Run simulation and basic hardware emulation \n\nWorkshop Outline▪ Versal ACAP Design Flow▪ Basic Hardware Design Process with the Vivado Design Suite▪ Demo: Packaging a Vivado design as an extensible platform▪ Driving the PetaLinux Tool▪ PetaLinux Tool Design Flow▪ Demo: Driving the PetaLinux tools▪ Vitis Simulation and Hardware emulation\n\nRegister TodayRegistration for this FREE Workshop at: Free Registration LOCATION:Online ORGANIZER;CN="Register online in our secure store": END:VEVENT could not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmplcould not find the >TEMPLATE_PHPICALENDAR_EVENT_ICS_ALLDAY< subpart-marker in fileadmin/templates/zwire/ext/cal/phpicalendar_event.tmpl END:VCALENDAR

 

**We have a new website in progress. Please email dcohen(at)fastertechnology.com for the current class schedule.

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes that are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.

Student Cancellation Policy

Student cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.

Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.

Student cancellations must be sent to registrar(at)fastertechnology.com

Faster Technology Course Cancellation Policy

Due to low class size and other certain considerations, Faster Technology may cancel a class up to 7 days before the scheduled start date of the class.  In such cases, all students will be entitled to a 100% refund.  Faster Technology will notify registered students of "at risk" classes prior to cancellation.

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Under no circumstances is Faster Technology responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.