Zynq UltraScale+MPSoC-Software Developer

Zynq UltraScale+MPSoC-Software Developer

EMBD-ZUPSW-ILT 

Course Description

This course provides software developers with an overview of the
capabilities and support for the Zynq® UltraScale+™ MPSoC family
from a software development perspective.
The emphasis is on:
▪ Reviewing the catalog of OS implementation options, including
hypervisors, and various Linux implementations
▪ Booting and configuring a system
▪ Applying various power management techniques for the Zynq
UltraScale+ MPSoC family

Level: Embedded Software 3 

Course Duration: 2 days 

Price: $1600 or 16 Xilinx Training Credits
Course Part Number: EMBD-ZUPSW-ILT 
Who Should Attend?: Software developers interested in understanding the OS and other capabilities of the Zynq UltraScale+MPSoC device.


Registration: Register online in our secure store

Prerequisites

  • General understanding of embedded and real-time operating systems
  • Familiarity with issues related to implementing a complex embedded system.

Software Tools

  •  Vivado Design Suite 2019.1
  • May require special Zynq UltraScale+MPSoC family license.

Hardware

  • VirtualBox
  • QEMU
  • Ubantu desktop
  • PetaLinux

* Host computer for running all the above software

 Contact us for the specifics of the in-class lab board or other customizations.

After completing this training , you will have the necessary skills to:

  • Distinguish between asymmetric multi-processing (AMP) and symmetric multi-processing (SMP)environments
  • Identify situations when the ARM TrustZone technology and/or a hypervisor should be used
  • Effectively use power management strategies and leverage the capabilities of the platform management unit (PMU)
  • Define the boot sequences appropriate to the needs of the system
  • Define the underlying implementation of the application processing unit(APU) and real-time processing unit(RPU) to make best use of their capabilities

Course Outline

Day 1

Application Processing Unit
Introduction to the members of the APU, specifically the
Cortex™-A53 processor and how the cluster is configured and
managed. {Lecture, Lab}
▪ Real-Time Processing Unit
Introduction to the various elements within the RPU and different
modes of configuration. {Lecture, Demo, Lab}
▪ ARM TrustZone Technology
Illustrates the use of the ARM® TrustZone technology. {Lecture}
▪ QEMU
Introduction to the Quick Emulator, which is the tool used to run
software for the Zynq UltraScale+ MPSoC device when hardware
is not available. {Lecture, Demo, Lab}
▪ HW-SW Virtualization
Covers the hardware and software elements of virtualization. The
lab demonstrates how hypervisors can be used. {Lecture, Demo,
Lab}
▪ MultiProcessor Software Architecture
Introduces several potential architectures and illustrate the
strengths of each. {Lecture}
▪ Hypervisors
Description of generic hypervisors and discussion of some of the
details of implementing a hypervisor using Xen. {Lecture, Demo,
Lab} (Pairs with OpenAMP, but not SMP)
▪ OpenAMP
Introduction to the concept of OpenAMP. {Lecture, Lab} (Pairs
with the Xen Hypervisor, but not SMP)
▪ Linux
Discussion and examples showing how to configure Linux to
manage multiple processors. {Lecture, Demo} 

Day 2

       Yocto
      Compares and contrasts the kernel building methods between a
      "pure" Yocto build and the PetaLinux build (which uses Yocto
      "under-the-hood"). {Lecture, Demo, Lab}
      ▪ Open Source Library (Linux)
      Introduction to open-source Linux and the effort and risk-reducing
      PetaLinux tools. {Lecture, Demo, Lab}
      ▪ FreeRTOS
      Overview of FreeRTOS with examples of how it can be used.
      {Lecture, Demo, Lab}
      ▪ Software Stack
      Introduction to what a software stack is and a number of stacks
      used with the Zynq UltraScale+ MPSoC. {Lecture, Demo}
      ▪ PMU
      Introduction to the concepts of power requirements in embedded
      systems and the Zynq UltraScale+ MPSoC. {Lecture, Lab}
      ▪ Power Management
      Overview of the PMU and the power-saving features of the
      device. {Lecture, Lab}

      Booting
      How to implement the embedded system, including the boot
      process and boot image creation. Also how to detect a failed boot.
      {Lecture, Lab}
      ▪ First Stage Boot Loader
      Introduction to the FSBL, its importance, and how it can be
      implemented and debugged. {Lecture, Demo, Lab}


      PDF version of this page.

      Enroll Now.

      Scheduled Embedded Courses

      Zynq UltraScale+MPSoC-Software Developer-Online
      December 16 - December 17: 09:00 am - 05:00 pm
      This two-day course is structured to provide software designers with a catalog of OS implementation...

      Embedded Design with PetaLinux Tools
      January 09 - January 10: 09:00 am - 05:00 pm
      v2017.3 This intermediate-level, two-day course provides embedded systems developers with...

      Designing FPGAs Using the Vivado Design Suite 2
      January 13 - January 14: 09:00 am - 05:00 pm
      This course shows you how to build an effective FPGA design using synchronous design techniques,...

      Embedded System Design
      January 16 - January 17: 09:00 am - 05:00 pm
      The course is designed to bring FPGA designers up to speed on developing embedded systems using the...

      Designing FPGAs Using the Vivado Design Suite 2
      January 23 - January 24: 09:00 am - 05:00 pm
      This course shows you how to build an effective FPGA design using synchronous design techniques,...

      Zynq SoC System Architecture 2018.1
      January 27 - January 28: 09:00 am - 05:00 pm
      * This course focuses on the Zynq-7000 SoC. Check with your local Authorized Training Provider for...

      Designing FPGAs Using the Vivado Design Suite 3- Dallas
      February 04 - February 05: 09:00 am - 05:00 pm
      This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

      Zynq UltraScale+MPSoC-Software Developer
      February 13 - February 14: 09:00 am - 05:00 pm
      This two-day course is structured to provide software designers with a catalog of OS implementation...

      Designing FPGAs Using the Vivado Design Suite 3
      February 18 - February 19: 09:00 am - 05:00 pm
      This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

      Alternative Dates and Locations

      Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.