Zynq UltraScale+MPSoC-Hardware Designer

Zynq UltraScale+MPSoC-Hardware Designer

Course Part Number-EMBD-ZUPHW-ILT 

Course Description

This two-day course is structured to provide hardware designers with an overview of many of the capabilities and support for the Zynq UltraScale+ MPSoC family from a hardware architectural perspective.

Level: Embedded Software 3 

Course Duration: 2 days 

Price: $1400 or 14 Xilinx Training Credits
Course Part Number: EMBDZUPHW-ILT 
Who Should Attend?: Hardware developers interested in understanding the Zynq UltraScale+ MPSoC device.


Registration: Register online in our secure store

Prerequisites

  • Suggested: Understanding of the Zynq-7000 architecture
  • Basic familiarity with embedded software development using C (to support testing of specific architectural elements)

Software Tools

  •  Vivado Design Suite 2015.4
  • May require special Zynq UltraScale+MPSoC family license.

Hardware

  • VirtualBox
  • QEMU
  • Ubantu desktop
  • PetaLinux

* Host computer for running all the above software

 Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training , you will have the necessary skills to:

  • Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
  • List the various power domains and how they are controlled
  • Describe the connectivity between the processing system (PS) and programmable logic(PL)
  • Utilize QEMU to emulate hardware behavior

Course Outline

  • Zynq UltraScale+MPSoC Application Processing Unit (Lecture,Lab)
  • Zynq UltraScale+MPSoC HW-SW Virtualization (Lecture,Lab) 
  • Zynq UltraScale+ MPSoC Real-Time Processing Unit (Lecture,Demo,lab)
  • Introduction to QEMU (Lecture,Demo,Lab)
  • Zynq UltraScale+ MPSoC Boot and Configuration (Lecture, Lab)
  • Zynq UltraScale+MPSoC System Protection (Lecture,Lab)
  • Zynq UltraScale+ MPSoC Clocks and Resets (Lecture,Lab)
  • Introduction to AXI (Lecture,Demo,Lab)
  • Zynq UltraScale + MPSoC PMU Hardware Perspective (Lecture,Lab)

Topic Descriptions

  • Zynq UltraScale+ MPSoC Application Processing Unit-Introduction to the members of the APU, Specifically the Cortex-A53 processor and how the cluster is configured and managed.
  • Zynq UltraScale+ HW-SW Virtualization-Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used.
  • Zynq UltraScale+MPSoC Real-Time Processing Unit-Introduction to the various elements within the RPU and different modes of configuration.
  • Introduction to the QEMU-Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available.
  • Zynq UltraScale+ MPSoC Boot and Configuration-How to implement the embedded system, including the boot process and boot image creation.
  • Zynq UltraScale+MPSoC System Protection-Covers all the hardware elements that support the separation of software domains.
  • Zynq UltraScale+MPSoC Clocks and Resets-Overview of clocking and reset, focusing more on capabilities than specific implementations.
  • Introduction to AXI-Understanding how the PS and PL connect enables designers to create more efficient systems.
  • Zynq UltraScale+MPSoC PMU Hardware Perspective-Overview of the PMU and the power-saving features of the device.


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Scheduled Embedded Courses

Zynq UltraScale+MPSoC-Software Developer-Online
October 24 - October 25: 09:00 am - 05:00 pm
v2017.1 This two-day course is structured to provide software designers with a catalog of OS...

Zynq UltraScale+MPSoC-System Architect-Online
October 26 - October 27: 09:00 am - 05:00 pm
v2017.1 This two-day online course is structured to provide system architects with an overview of...

Designing FPGAs Using the Vivado Design Suite 2
November 07 - November 08: 09:00 am - 05:00 pm
v2017.1 This course shows you how to build an effective FPGA design using synchronous design...

Designing FPGAs Using the Vivado Design Suite 3
November 09 - November 10: 09:00 am - 05:00 pm
This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

Designing FPGAs Using the Vivado Design Suite 4
November 28 - November 29: 09:00 am - 05:00 pm
This course tackles the most sophisticated aspects of the Vivado Design Suite and Xilinx hardware....

Zynq UltraScale+MPSoC-Software Developer-Online
December 06 - December 07: 09:00 am - 05:00 pm
v 2016.3 This two-day course is structured to provide software designers with a catalog of OS...

Zynq UltraScale+MPSoC-System Architect-Online
December 12 - December 13: 09:00 am - 05:00 pm
This two-day online course is structured to provide system architects with an overview of the...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.