Zynq UltraScale+MPSoC-Hardware Designer

Zynq UltraScale+MPSoC-Hardware Designer

Course Part Number-EMBD-ZUPHW

Course Description


This course provides hardware designers with an overview of the
capabilities and support for the Zynq® UltraScale+™ MPSoC family
from a hardware architectural perspective.
The emphasis is on:
▪ Identifying the key elements of the application processing unit
(APU) and real-time processing unit (RPU)
▪ Reviewing the various power domains and their control structure
▪ Illustrating the processing system (PS) and programmable logic
(PL) connectivity
▪ Utilizing QEMU to emulate hardware behavior

Level: Embedded Software 3 

Course Duration: 2 days 

Price: $1600 or 16 Xilinx Training Credits
Course Part Number: EMBDZUPHW-ILT 
Who Should Attend?: Hardware developers interested in understanding the Zynq UltraScale+ MPSoC device.


Registration: Register online in our secure store

Prerequisites

  • Suggested: Understanding of the Zynq-7000 architecture
  • Basic familiarity with embedded software development using C (to support testing of specific architectural elements)

Software Tools

  •  Vivado Design Suite 2019.1
  • May require special Zynq UltraScale+MPSoC family license

Hardware

  • VirtualBox
  • QEMU
  • Ubantu desktop
  • PetaLinux
  • Zynq UltraScale+ MPSoC ZCU104 board*

 Contact us for the specifics of the in-class lab board or other customizations.


* This course focuses on the Zynq UltraScale+ MPSoC architecture.
Check with your local Authorized Training Provider for the specifics of
the in-class lab environment or other customizations. This version of
the class does not use a physical board, but rather a local emulation
environment and the Vivado Design Suite

After completing this comprehensive training , you will have the necessary skills to:

  • Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
  • List the various power domains and how they are controlled
  • Describe the connectivity between the processing system (PS) and programmable logic(PL)
  • Utilize QEMU to emulate hardware behavior

Course Outline

Day 1

▪ Application Processing Unit
Introduction to the members of the APU, specifically the
Cortex™-A53 processor and how the cluster is configured and
managed. {Lectures, Lab}
▪ HW-SW Virtualization
Covers the hardware and software elements of virtualization. The
lab demonstrates how hypervisors can be used. {Lectures, Demo,
Lab}
Real-Time Processing Unit
Focuses on the real-time processing module (RPU) in the PS,
which is comprised of a pair of Cortex processors and supporting
elements.. {Lectures, Demo, Lab}
QEMU
Introduction to the Quick Emulator, which is the tool used to run
software for the Zynq UltraScale+ MPSoC device when hardware
is not available. {Lectures, Demos}
▪ Booting
How to implement the embedded system, including the boot
process and boot image creation. {Lectures, Lab}
▪ First Stage Boot Loader
Demonstrates the process of developing, customizing, and
debugging this mandatory piece of code. {Lecture, Demo}


Day 2

  Video
Introduction to video, video codecs, and the Video Codec Unit
available in the Zynq UltraScale MPSoC. {Lectures}
▪ System Protection
Covers all the hardware elements that support the separation of
software domains. {Lectures}
▪ Clocks and Resets
Overview of clocking and reset, focusing more on capabilities
than specific implementations. {Lectures, Demos}
▪ AXI
Understanding how the PS and PL connect enables designers to
create more efficient systems. {Lectures, Demo, Lab}
▪ Power Management
Overview of the PMU and the power-saving features of the device {Lecture. Lab}

 

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Scheduled Embedded Courses

Designing FPGAs Using the Vivado Design Suite 2
January 23 - January 24: 09:00 am - 05:00 pm
This course shows you how to build an effective FPGA design using synchronous design techniques,...

Zynq SoC System Architecture 2018.1
January 27 - January 28: 09:00 am - 05:00 pm
* This course focuses on the Zynq-7000 SoC. Check with your local Authorized Training Provider for...

Designing FPGAs Using the Vivado Design Suite 3
February 18 - February 19: 09:00 am - 05:00 pm
This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

Zynq UltraScale+MPSoC-Software Developer
February 27 - February 28: 09:00 am - 05:00 pm
This two-day course is structured to provide software designers with a catalog of OS implementation...

Zynq UltraScale+MPSoC-Software Developer
March 03 - March 04: 09:00 am - 05:00 pm
v2016.3 This two-day course is structured to provide software designers with a catalog of OS...

Zynq UltraScale+MPSoC-System Architect
March 05 - March 06: 09:00 am - 05:00 pm
This two-day online course is structured to provide system architects with an overview of the...

Zynq UltraScale+MPSoC-Software Developer
March 12 - March 13: 09:00 am - 05:00 pm
This two-day course is structured to provide software designers with a catalog of OS implementation...

Designing FPGAs Using the Vivado Design Suite 3- Dallas
March 19 - March 20: 09:00 am - 05:00 pm
This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

Zynq UltraScale+MPSoC-System Architect
April 02 - April 03: 09:00 am - 05:00 pm
* This course focuses on the Zynq UltraScale+ MPSoC architecture. Check with your local Authorized...

Zynq UltraScale+MPSoC-Software Developer-Online
April 09 - April 10: 09:00 am - 05:00 pm
This two-day course is structured to provide software designers with a catalog of OS implementation...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.