Zynq All Programmable SoC System Architecture

EMBD-ZSA-ILT | EMBD24000-ILT (v1.0)

Course Description

The Xilinx Zynq™ All Programmable System on a Chip (SoC) provides a new level of system design capabilities. This course provides system architects with the knowledge to effectively architect a Zynq All Programmable SoC .

This course presents the features and benefits of the Zynq architecture for making decisions on how to best architect a Zynq All Programmable SoC project. It covers the architecture of the ARM® Cortex™-A9 processor-based processing system (PS) and the connections to the programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq All Programmable SoC.

The course also details the individual components that comprise the PS, I/O peripherals, timers, and caching, DMA, interrupt, and memory controllers. Emphasis will be placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, trade offs, and advantages of implementing functions in the PS or the PL.

Level: Embedded Architect 3
Course Duration: 2 days
Price: $1400 or 14 Xilinx Training Credits
Course Part Number: EMBD24000-ILT
Who Should Attend?: System architects who are interested in architecting a system on a chip using the Zynq All Programmable SoC.
Registration: Register online in our secure store

Prerequisites

  • Digital system architecture design experience
  • Basic understanding of microprocessor architecture
  • Basic understanding of C programming
  • Basic HDL modeling experience

Software Tools

  •  Vivado Design or System Edition 2015.1

Hardware

  • Architecture: Zynq-7000 All Programmable SoC*
  • Demo board: Zynq-7000 All Programmable SoC ZC702 or Zed board*

* This course focuses on the Zynq-7000 All Programmable SoC. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the architecture and components that comprise the Zynq All Programmable SoC processing system (PS)
  • Relate a user design goal to the function, benefit, and use of the Zynq All Programmable SoC
  • Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals
  • Analyze the tradeoffs and advantages of performing a function in software versus PL

Course Outline

Day 1

  • Zynq All Programmable SoC Overview
  • Inside the Application Processor Unit (APU)
  • Lab 1: Building a Zynq All Programmable SoC Platform
  • Processor Input/Output Peripherals
  • Introduction to AXI
  • Zynq All Programmable SoC PS/PL Interfaces
  • Lab 2: Integrating Programmable Logic on the Zynq All Programmable SoC
  • Zynq All Programmable Soc Booting
  • Lab 3: Using DMA on the Zynq All Programmable SoC

Day 2

  • Zynq All Programmable SoC Memory Resources
  • Meeting Performance Goals
  • Lab 4: Impact of Port Selection on System Performance
  • Zynq All Programmable SoC Hardware Design
  • Zynq All Programmable SoC Software Design
  • Debugging the Zynq All Programmable SoC
  • Lab 5: Debugging on the All Programmable SoC
  • Zynq All Programmable SoC Tools and Reference Designs
  • Lab 6: Running and Debugging a Linux Application on the Zynq All Programmable SoC

Lab Descriptions

  • Lab 1: Building a Zynq All Programmable SoC Platform – Examine the process of using the Vivado IP Integrator tool to create a simple processing system.
  • Lab 2: Integrating Programmable Logic on the Zynq All Programmable SoC – Connect a programmable logic (PL) design to the embedded processing system (PS).
  • Lab 3: Using DMA on the Zynq All Programmable SoC – Experiment with effectively using the PS DMA controller to move data between DDRx memory and a custom PL peripheral.
  • Lab 4: Impact of Port Selection on system Performance- Explore bandwidth issues surrounding the use of the Accelerator Coherency Port (ACP) and the High Performance (HP) ports.
  • Lab 5: Debugging on the Zynq All Programmable SoC – Evaluate debugging the hardware and software components of a Zynq All Programmable SoC design.
  • Lab 6: Running and Debugging a Linux Application on the Zynq All Programmable SoC – Explore a software application executing under the Linux operating system on the Zynq All Programmable SoC.

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Scheduled Embedded Courses

Zynq UltraScale+MPSoC-Software Developer-Online
October 24 - October 25: 09:00 am - 05:00 pm
v2017.1 This two-day course is structured to provide software designers with a catalog of OS...

Zynq UltraScale+MPSoC-System Architect-Online
October 26 - October 27: 09:00 am - 05:00 pm
v2017.1 This two-day online course is structured to provide system architects with an overview of...

Designing FPGAs Using the Vivado Design Suite 2
November 07 - November 08: 09:00 am - 05:00 pm
v2017.1 This course shows you how to build an effective FPGA design using synchronous design...

Designing FPGAs Using the Vivado Design Suite 3
November 09 - November 10: 09:00 am - 05:00 pm
This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

Designing FPGAs Using the Vivado Design Suite 4
November 28 - November 29: 09:00 am - 05:00 pm
This course tackles the most sophisticated aspects of the Vivado Design Suite and Xilinx hardware....

Zynq UltraScale+MPSoC-Software Developer-Online
December 06 - December 07: 09:00 am - 05:00 pm
v 2016.3 This two-day course is structured to provide software designers with a catalog of OS...

Zynq UltraScale+MPSoC-System Architect-Online
December 12 - December 13: 09:00 am - 05:00 pm
This two-day online course is structured to provide system architects with an overview of the...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.