UltraFast Design Metholology

UltraFast Design Methodology

FPGA 3 | FPGA VDM

Course Description

This course describes the FPGA design best practices and skills to be successful using the Vivado® Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an FPGA design methodology case study. The UltraFast design metholology checklist is also introduced.

Level: FPGA 3 
Course Duration: 1 day
Price: $700 or 7 Xilinx Training Credits
Course Part Number: FPGA-VDM-ILT 
Who Should Attend?:Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.
Registration: Register online in our secure store

Prerequisites

  • Some knowledge of FPGA design techniques is helpful
  • Experience with the Vivado Design Suite or attendance of one of our existing Vivado Design Suite training courses is required
  • Intermediate knowledge of Verilog or VHDL

Software Tools

  • Vivado Design or System Edition 2016.1

Hardware

  • Architecture: UltraScale and 7 series FPGAs*
  • Demo board: None

*This course focuses on the 7 series FPGA architectures. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

 

  • Describe the Vivado Design Suite FPGA Design Methodology Checklist
  • Identify key areas to optimize your design to meet your design goals and performance objectives
  • Define a properly constrained design
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
  • Build resets into your system for optimum reliability and design speed
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Identify timing closure techniques using the Vivado Design Suite
  • Describe how the UltraFast design metholology techniques work effectively through case studies and lab experience. 

Course Outline

  • UltraFast Design Methodology Case Study
  • Demo 1: UltraFast Design Methodology Checklist
  • UltraFast Design Metholology
  • HDL Coding Techniques
  • Resets
  • Lab 1: Resets
  • Inference
  • Lab 2: Inference
  • Synchronization Circuits
  • Demo 2: Synchronization Circuits
  • Baselining
  • Demo 3: Baselining
  • Timing Closure and Desing Conversion Lab Introduction
  • Lab 3: Timing Closure and Design Conversion 
  • Pipelining
  • Lab 4: Pipelining
  • Register Duplication
  • Physical Optimization
  • I/O Flip-Flops

Lab Descriptions

  • Lab 1: Resets – Investigate the proper design and use of resets. Examine the impact of seeing a design built originally with asynchronous resets, having resets removed, and finally with synchronous resets only used where necessary.
  • Lab 2: Inference -- Evaluate the implementation results of a design that uses asynchronous resets and infers more dedicated hardware resources when resets are selectively removed from the design. You will also learn how to infer the DSP hardware resources for other common functions required by most FPGA designs.
  • Lab 3: Timing Closure and Design Conversion – Learn how a generic processor design was optimized for the 7 series device architecture with basic design changes that impacted the dedicated hardware usage, design speed, and the device utilization.
  • Lab 4: Pipelining-- Explore how pipelining can improve performance (increased clock rate and throughput) and facilitate timing closure.

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Scheduled FPGA Courses

DARPA PRIVATE--High-Level Synthesis with the Vivado HLS Tools-Dallas
September 13 - September 14: 09:00 am - 05:00 pm
v2017.1 This course provides a through introduction to the Vivado High-Level Synthesis (HLS) tool....

Designing FPGAs Using the Vivado Design Suite 1-Dallas
September 27 - September 28: 09:00 am - 05:00 pm
This course offers introductory training on the Vivado Design Suite and helps you to understand the...

C-Based Design: High-Level synthesis with the Vivado HLx Tool
October 10 - October 11: 09:00 am - 05:00 pm
v2017.1 This course provides a through introduction to the Vivado High-Level Synthesis (HLS) tool....

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.