Xilinx Partial Reconfiguration Tools and Techniques

FPGA-PR-ILT

Course Description

This course demonstrates how to use the Vivado® Design Suite to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow. This course also demonstrates how to use thee PR controller and PR decoupler IP in the PR process. You will also gain an understanding of PR implementation in an embedded system environment.

This course covers both the tool flow and mechanics of successfully creating a PR design. This course also covers both UltraScale™ and 7 series architecture design requirements, recommendations, and expectations for PR systems. In addition, it describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications. You will also identify techniques to debug PR designs. 

Level: FPGA4
Course Duration: 2 days
Price: $1400 or 14 Xilinx Training Credits
Course Part Number: FPGA-PR-ILT
Who Should Attend?: Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who have need of partial reconfiguration techniques
Registration: Register online in our secure store

Prerequisites

 

  • Designing FPGAs with the Vivado Design Suite 2 course 
  • Designing FPGAs with the Vivado Design Suite 3 course 
  • Designing FPGAs with the Vivado Design Suite 4 course 
  • Working HDL knowledge (VHDL or Verilog) 

Software Tools

  • Vivado Design or System Edition 2017.3

Hardware

 

  • Architecture: UltraScale and 7 series FPGAs* 
  • Demo board: Kintex® UltraScale FPGA KCU105 board, Kintex-7 FPGA KC705 board, and ZedBoard** 

After completing this comprehensive training, you will have the necessary skills to:

    • Build and assemble a Partially Reconfigurable system (UltraScale, 7 series, and Zynq® devices) Define PR regions and reconfigurable modules with the Vivado Design Suite
    • Generate the appropriate full and partial bitstreams for a PR design 
    • Use the ICAP and PCAP components to deliver the partially reconfigurable systems
    • Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, clock buffers, and MGTs 
    • Implement a Partial Reconfiguration system using the following techniques: ○ Direct JTAG connection ○ Floorplanning ○ Timing constraints and analysis
    • Implement a PR system using the PRC IP 
    • Implement a PR system in an embedded environment
    • Debug PR designs 

    Course Outline

    Day 1

     

    • Introduction to Partial Reconfiguration 
    • Demo: Introduction to Partial Reconfiguration 
    • Partial Reconfiguration Flow 
    • Lab 1: Partial Reconfiguration Tool Flow 
    • Lab 2: Partial Reconfiguration Project Flow 
    • Lab 3: Floorplanning the PR Design 
    • Partial Reconfiguration Design Considerations 
    • Optional: FPGA Configuration Overview 
    • Partial Reconfiguration Bitstreams 
    • Demo: Partial Reconfiguration Controller (PRC) IP 
    • Lab 4: Using the Partial Reconfiguration Controller in a PR Design 

    Day 2

     

    • Partial Reconfiguration: Managing Timing 
    • Lab 5: Partial Reconfiguration Timing Analysis and Constraints 
    • Partial Reconfiguration in Embedded Systems 
    • Lab 6: Partial Reconfiguration in Embedded Systems 
    • Debugging Partial Reconfiguration Designs 
    • Lab 7: Debugging a Partial Reconfiguration Design 
    • Partial Reconfiguration Design Recommendations 
    • PCIe Core and Partial Reconfiguration 

    Lab Descriptions

     

    • Lab 1: Partial Reconfiguration Tool Flow – Illustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will download a partial bitstream to the demo board via the JTAG connection. 
    • Lab 2: Partial Reconfiguration Project Flow – Illustrates Partial Reconfiguration (PR) project flow in the Vivado® Design Suite. At the end of this lab, you will be able to create multiple RMs and configurations using Partial Reconfiguration Wizard. 
    • Lab 3: Floorplanning the PR Design – Illustrates how to create efficient Pblocks for a Partial Reconfiguration design. At the end of this lab, you will understand the impact of the SNAPPING_MODE property for a Pblock. 
    • Lab 4: Using the Partial Reconfiguration Controller in a PR Design – Illustrates using the PRC IP and hardware triggers to manage partial bitstreams. 
    • Lab 5: Partial Reconfiguration Timing Analysis and Constraints – Shows how area groups and Reconfigurable Partitions affect design performance. 
    • Lab 6: Partial Reconfiguration in Embedded Systems – Illustrates implementing PR designs in an embedded environment. 
    • Lab 7: Debugging a Partial Reconfiguration Design – Demonstrates using ILA cores to debug PR designs and shows which signals to monitor during debugging.  

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    Scheduled FPGA Courses

    C-Based Design: High-Level synthesis with the Vivado HLx Tool
    May 24 - May 25: 09:00 am - 05:00 pm
    v2017.1 This course provides a through introduction to the Vivado High-Level Synthesis (HLS) tool....

    Designing FPGAs Using the Vivado Design Suite 4
    June 12 - June 13: 09:00 am - 05:00 pm
    This course tackles the most sophisticated aspects of the Vivado Design Suite and Xilinx hardware....

    Alternative Dates and Locations

    Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.