Debugging Techniques Using the Chipscope Pro Tools

FPGA 2 | CSP22000-ILT (v1.0)

Course Description

As FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for verification and debug.

This two-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This Xilinx Chipscope training will provide hands-on labs that demonstrate how the tools can address advanced verification and debugging challenges.

Level: FPGA 2
Course Duration: 2 days
Price: $1400 or 14 Xilinx TCs
Course Part Number: CSP22000-ILT
Who Should Attend?:System and logic designers who want to minimize verification and debug time
Registration: Register online in our secure store


  • Design for Performance or Vivado Static Timing Analysis and Xilinx Design Constraints
  • Chipscope Pro Software REL strongly recommended

Software Tools

  • Xilinx ISE® Design Suite: Logic or System Edition 14.2
  • ChipScope Pro tool 14.2
  • Vivado System Edition 2012.2 (optional)


  • Architecture N/A
  • Demo boards: Kintex-7 FPGA KC705 board

After completing this comprehensive course, you will have the necessary skills to:

  • Identify each ChipScope Pro tool core and explain its purpose
  • Effectively utilize the ChipScope Pro Analyzer and Vivado Analyzer tool
  • Implement the ChipScope Pro tool using the CORE Generator™, Core Inserter, and PlanAhead™ tool flows
  • Select effective test points in your design
  • Optimize design and core performance when ChipScope Pro tool cores are used
  • Execute various techniques for collecting data, including file storage, scripting, and building custom triggers

Course Outline

Day 1

  • How the ChipScope Pro Tool Works
  • Inserting the Cores – Inserter Flows: Core Inserter, PlanAhead, Vivado Tools
  • Labs 1 and 2: Using the Inserter Tool from PlanAhead Design Environment or Vivado Design Suite
  • Instantiating the Cores – The CORE Generator Tool Flow
  • Lab 3: Using the CORE Generator Tool from PlanAhead Design Environment
  • Triggering and Storage
  • Visualizing Data – The ChipScope Pro Analyzer Tool
  • Lab 4: Triggering and Visualization in the Analyzer Tool

Day 2

  • Tips and Tricks
  • Lab 5: Tips and Tricks
  • Time for Timing
  • Video Demo – Area Groups for Isolation
  • Case Studies
  • Lab 6: FPGA Editor Support for the ChipScope Pro Tool
  • Scripting (Optional)*
  • Lab 7: Remote Access (Optional)*
  • Lab 8: Remote Access*

* Check with your local ATP to confirm whether this content is included with your specific class.

Lab Descriptions

  • Labs 1 and 2: Using the Inserter Tool from Planahead Design Environment or vivado Design Suite--Insert ICON and ILA cores into an existing netlist and debug a common problem.
  • Lab 3: Using the CORE Generator Tool from PlanAhead Design Environment – Build upon a provided design to create and instantiate a VIO core and observe its behavior using the ChipScope Pro Analyzer tool.
  • Lab 4: Triggering and Visualization in the Analyzer Tool – Configure triggers and view captured data using the ChipScope Pro Analyzer tool.
  • Lab 5: Tips and Tricks – Keep time across multiple sample windows; sample across multiple time domains.
  • Lab 6: FPGA Editor Support for the ChipScope Pro Tool – Change the signals being sampled by an ILA without having to reimplement the design.
  • Lab 7: Remote Access – Use the ChipScope Pro Analyzer tool to configure an FPGA, set up triggering, and view the sampled data from a remote location.

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Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.