How to Design a Xilinx Digital Signal Processing System in 1 Day

DSP 2 | DSP13000-13-ILT (v1.0)

Course Description

The workshop introduces you to fundamental DSP concepts, algorithms, and techniques for implementation in Xilinx FPGAs. Design examples and labs are drawn from several common applications spaces, including wireless communications, video, and imaging.

Only essential theory is introduced in order to lay a foundation for the material and topics covered in this workshop, which complements more detailed training found in subsequent Xilinx courses.  

The material is also complementary to the Avnet SpeedWay Design Workshop on FPGA-Based System Design with High-Speed Data Converters.

Level: DSP 2
Course Duration: 1 days
Price: $700 or 7 Xilinx Training Credits
Course Part Number: DSP13000-13-ILT
Who Should Attend?: FPGA designers and logic designers
Registration: Register online in our secure store

Prerequisites

  • VHDL or Verilog experience or Designing with VHDL or Designing  with Verilog course
  • FPGA design experience or Essentials of FPGA Design course
  • Fundamental understanding of digital signal processing theory
  • Fundamental understanding of FIR filter and FFT theory 
  • Very basic understanding of FPGA architecture

Software Tools

  • Xilinx ISE® Design Suite: DSP or System Edition 13.1

Hardware

  • Architecture: Spartan®-6 and Virte®x-6 FPGAs*
  • Demo board: Spartan-6 FPGA SP605 or Virtex-6 FPGA ML605 board*

* This workshop focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Describe some fundamental DSP concepts, algorithms and techniques for implementation in Xilinx FPGAs
  • Recognize how both the CLB slices in FPGAs and the more advanced DSP48s are used to implement DSP algorithms
  • Identify the contents and operation of the Xilinx FPGA DSP Targeted Design Platform (TDP)
  • Construct typical DSP designs using the Xilinx design and simulation tools  and implement these designs on target hardware
  • Identify additional courses and workshops to further your training with Xilinx devices

Course Outline

  • Workshop Overview
  • Virtex-6 and Spartan-6 FPGA Architecture
  • DSP Essentials
  • Lab 1: Introduction to System Generator
  • System Generator Design Flow
  • Lab 2: Filter and  FFT Design
  • FFT Basics
  • Lab 3: DSP Targeted Design Platform
  • Video and Imaging IP
  • Lab 4: Video Processing  and Shared Memory

Lab Descriptions

  • Lab 1: Introduction to System Generator – In this lab, you will create a simple modulation system that will consist of a Direct Digital Synthesizer (DDS) module for generating a sine wave and a multiplier created using a DSP48.
  • Lab 2: Filter and FFT Design – In this lab, two important blocks are examined: the FIR Compile and FFT. The design includes serialization of parallel data and up sampling and filtering the data. The lab also presents how to use and configure the FFT block.
  • Lab 3: DSP Targeted Design Platform – This lab illustrates a WCDMA single carrier DUC / DDC design based on a reference design in Application Note XAPP1018. Hardware co-simulation is also performed.
  • Lab 4: Video Processing and Shared Memory – This lab demonstrates using DSP System Generator in a video processing design as well as utilizing hardware co-simulation with shared memory.

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Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.