FPGA Power Optimization

After completing this comprehensive training, you will have the necessary skills to:

• Use Xilinx Power Estimator spreadsheet to estimate your design’s power consumption at the concept phase
• Use the Xilinx Power Analyzer to estimate your design’s power consumption after implementation has been completed
• Import Activity Rates to complete a dynamic power estimation
• Use the synthesis and implementation options to reduce your design’s power consumption
• Use optimum HDL coding techniques and design practices to reduce your design’s power consumption
• Take advantage of the Virtex-7 architecture features that reduce power consumption

Course Outline

• Introduction
• FPGA Power Requirements
• Xilinx Power Estimator Spreadsheet (XPE)
• Lab 1: Power Estimation with XPE
• Xilinx Power Analyzer
• Lab 2: Power Estimation with XPA
• Lab 3: Dynamic Power Estimation
• Power Management Software Options
• Lab 4: Power Management Software Options
• Power Management Design Techniques
• Power Optimization of I/O Resources
• 7 Series Power Management Features
• How to Solve a Power Problem
• Worse-Case Thermal Calculations (optional)
• Spartan-6 FPGA Power Management Features (optional)
• Virtex-6 FPGA Power Management Features (optional)
• Power and Temperature Measurement Features (optional)
• Introduction to Partial Reconfiguration (optional)

Lab Descriptions

• Lab 1: Power Estimation with XPE – Estimate the resources required based on the high-level design description. Enter the amount of resources and default activity rates for the design and evaluate the estimated power calculated by XPE.
• Lab 2: Power Estimation with XPA –  Import the MAP report contents into the XPE spreadsheet and evaluate the estimated power with the XPE. Estimate the design’s power consumption with the XPA power estimation utility and compare its results to that made with XPE.
• Lab 3: Dynamic Power Estimation – Simulate the design with ISim and generate the necessary Switching Activity Interchange Format (SAIF) file. Launch the XPA utility, load the SAIF file contents, and use XPA to estimate your design’s dynamic power consumption.
• Lab 4: Power Management Software Options – Use the Power reduction option in MAP and the Global Optimization settings to save power in your design.

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Scheduled FPGA Courses

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.