Embedded C/C++ SDSoC Development Environment and Methodology

Embedded C/C++ SDSoC Development Environment and Methodology

Course Part Number-EMBD-SDSOC-ILT 

Course Description

This one-day course is structured to help designers new to the SDSoC development environment to quickly create accelerated systems. The focus is on utilizing the tools to accelerate an existing design at the system architecture level, not on the optimization of the accelerator microarchitectures.

Level: Embedded 1 (morning), Embedded 2 (Afternoon) 

Course Duration: 1 day 

Price: $1400 or 14 Xilinx Training Credits
Course Part Number: EMBD-SDSOC-ILT 
Who Should Attend?: Anyone interested in quickly adding hardware acceleration to a software system.


Registration: Register online in our secure store

Prerequisites

  • Understanding of Zynq-7000 architecture (with emphasis on ACP,HP ports, and internal routing)
  • Comfort with C programming language
  • Familiarity with the Vivado Design Suite, Vivado HLS tool, and Xilinx SDK

Software Tools

  • SDSoC development environment 2016.2

Hardware

  • Architecture: Zynq-7000 All Programmable SoC
  • Demo Board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard

This course focuses on the Zynq-7000 All Programmable SoC.

 Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training , you will have the necessary skills to:

  • Identify candidate functions for hardware acceleration by using the TCF profiling tool
  • Use the System Debugger's capabilities to control the execution flow and examine memory and variables during a debug session.
  • Move designated software functions to hardware and estimate the performance of the accelerator and the effect on the entire system
  • Override tool and defaults to improve the performance of the individual accelerators and the overall system

Course Outline

  • Zynq AP SoC Architecture Support for Accelerators (optional)
  • Software Overview (Optional)
  • SDSoC Tool Overview (Lecture,Two Demos,Lab)
  • SDSoC Tool Design Best Practices (Lecture,Lab)
  • Application Profiling (Lecture,Demo,Lab)
  • Application Debugging (Lecture,Demo,Lab)
  • Understanding Estimations in the SDSoC Tool (Lecture,Demo,Lab)
  • Blocking vs Non-Blocking Implementations in the SDSoC Tool (Lecture,Lab)
  • Implementing Multiple Accelerators in the SDSoC Tool (Lecture,Two Lab)
  • SDSoC Platform Creation (Lecture, Lab)
  • Hardware/Software Event Tracing (Lecture, Lab)

Topic Descriptions

  • Zynq AP SoC Architecture Support for Accelerators (Optimal)-Discusses the relevant aspects of the Zynq All Programmable SoC architecture for accelerator design. The focus is on AXI ports and protocols, system latency, and memory utilization.
  • Software Overview(Optional)-Provides a though understanding of how the integrated design environment works, including how the compiler and linker behave, basics of makefiles, DMA usage, and variable scope.
  • SDSoC Tool Overview (Lecture,Demos,Lab)-Introduces the purpose, underlying structures,and basic functionality of the SDSoC development environment through a combination of SDSoC development environment through a combination of lecture and demonstration. Student will cement their knowledge with a lab that reinforces the concepts provided in the lecture and demo.
  • SDSoc Design Best Practices (Lecture,Demo)-Illustrates common mistakes and how to avail them. Also describes approaches to refactoring software for hardware acceleration.
  • Application Profiling (Lecture,Demo,Lab)-Profiling is the process that identifies how the processor is spending its time. Through profiling, the user can quickly identify which functions must be optimized or moved to hardware to satisfy the performance requirements.
  • Application Debugging (Lecture,Demo,Lab)-Through the use of the System Debugger, students will learn how to follow the control flow in an executing application and see the effects of the code on memory to successfully debug software issues.
  • Understanding Estimations in the SDSoC Tool (Lecture,Demo,Lab)-Once a function is moved to hardware, questions remain: Will the accelerator fit in hardware? Will it run fast enough? Estimations can provide the answers.
  • Blocking and Non-Blocking Implementations in the SDSoC tool (Lecture,Lab)-Addresses how the processor behaves while the accelerator is producing solutions-does it wait or continue on?
  • Implementing Multiple Accelerators in the SDSoC Tool (Lecture,Lab)-There are times when moving a single function to hardware is not enough-multiple functions must be moved to hardware, or one accelerator must be duplicated. Here students will learn to control how the tool produces the accelerators.
  • SDSoC Platform Creation (Lecture, Lab)- Describes how to create a custom SDSoC platform starting from a hardware system built using the Vivado Design Suite, and a software run-time environment, including operating system kernel, boot loaders, file system, and libraries.
  • Hardware/Software Event Tracing (Lecture, Lab)- Hardware/software event trace helps the user to understand the performance of their application given the workload, hardware/software partitioning, and system design choices. Such information helps the user to optimize and improve system implementation.


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Scheduled Embedded Courses

Zynq UltraScale+MPSoC-Software Developer-Online
October 24 - October 25: 09:00 am - 05:00 pm
v2017.1 This two-day course is structured to provide software designers with a catalog of OS...

Zynq UltraScale+MPSoC-System Architect-Online
October 26 - October 27: 09:00 am - 05:00 pm
v2017.1 This two-day online course is structured to provide system architects with an overview of...

Designing FPGAs Using the Vivado Design Suite 2
November 07 - November 08: 09:00 am - 05:00 pm
v2017.1 This course shows you how to build an effective FPGA design using synchronous design...

Designing FPGAs Using the Vivado Design Suite 3
November 09 - November 10: 09:00 am - 05:00 pm
This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

Designing FPGAs Using the Vivado Design Suite 4
November 28 - November 29: 09:00 am - 05:00 pm
This course tackles the most sophisticated aspects of the Vivado Design Suite and Xilinx hardware....

Zynq UltraScale+MPSoC-Software Developer-Online
December 06 - December 07: 09:00 am - 05:00 pm
v 2016.3 This two-day course is structured to provide software designers with a catalog of OS...

Zynq UltraScale+MPSoC-System Architect-Online
December 12 - December 13: 09:00 am - 05:00 pm
This two-day online course is structured to provide system architects with an overview of the...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.